參數(shù)資料
型號: W83977CTF-PW
英文描述: PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述: 周邊(多功能)控制器
文件頁數(shù): 131/161頁
文件大?。?/td> 592K
代理商: W83977CTF-PW
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-122 -
Revision A1
Bit 2: FDCTRAPSTS. FDC trap status.
= 0
FDC is now in the sleeping state.
= 1
FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, or any enabling of the motor enable bits in the DOR register.
Bit 1: URATRAPSTS. UART A trap status.
= 0
UART A is now in the sleeping state.
= 1
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting a
start bit, or any transition on MODEM control input lines.
Bit 0: URBTRAPSTS. UART B trap status.
= 0
UART B is now in the sleeping state.
= 1
UART B is now in the workinging state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting a
start bit, or any transition on MODEM control input lines.
CRF3 (Default 0x00)
Bit 7: Reserved. Return zero when read.
Bit 6 - 0: Device's IRQ status.
These bits indicate the IRQ status of the individual device respectively. The device's IRQ status
bit
is set by their source device and is cleared by writing a 1. Writing a 0 has no effect.
Bit 6: URCIRQSTS. UART C IRQ status.
Bit 5: MOUIRQSTS. MOUSE IRQ status.
Bit 4: KBCIRQSTS. KBC IRQ status.
Bit 3: PRTIRQSTS. printer port IRQ status.
Bit 2: FDCIRQSTS. FDC IRQ status.
Bit 1: URAIRQSTS. UART A IRQ status.
Bit 0: URBIRQSTS. UART B IRQ status.
CRF4 (Default 0x00)
Bit 7 - 5: Reserved. Return zero when read.
Bit 3: Reserved. Return zero when read.
Bit 4 and Bit 2 - 0:These bits indicate the status of the individual GPIO function respectively. The
status is set by their source function and is cleared by writing a 1. Writing a 0 has no effect.
Bit 4: WDTIRQSTS. Watch dog timer IRQ status at logical device 8.
Bit 2: COMIRQSTS. Common IRQ status of GP20 - GP25 at logical device 8.
Bit 1: GP11IRQSTS. GP11 interrupt steering status at logical device 7.
Bit 0: GP10IRQSTS. GP10 interrupt steering status at logical device 7.
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