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參數(shù)資料
| 型號： | W83196R-718 |
| 英文描述： | VIA Buffer Chip(4*DDR or 2*DDR + 3*SDRAM) |
| 中文描述： | 威盛緩沖芯片（4 * DDR或2 * 3 *的DDR SDRAM內(nèi)存） |
| 文件頁數(shù)： | 5/13頁 |
| 文件大小： | 731K |
| 代理商： | W83196R-718 |
W83194BR-250
4.3 I
2
C Control Interface
SYMBOL
PIN
I/O
FUNCTION
SDATA*
29
I/O
Serial data of I
2
C 2-wire control interface
Serial clock of I
2
C 2-wire control interface
SDCLK*
28
IN
4.4 Fixed Frequency Outputs
SYMBOL
PIN
I/O
FUNCTION
REF0
48
OUT
3.3V 14.318MHz reference clock.
REF1 / *FS4
47
I/O
14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Latched input for FS4 at initial power up for H/W
selecting the output frequency of CPU,
AGP
and PCI
clocks (Default=1).
24_48MHz/FS2*
7
I/O
24MHz or 48MHz output clock.
Latched input for FS42at initial power up for H/W
selecting the output frequency of CPU,
AGP
and PCI
clocks (Default=1).
48MHz_1/ FS3*
6
I/O
48MHz / Latched input for FS3 at initial power up
for H/W selecting the output frequency of CPU,
AGP
and PCI clocks (Default=1).
4.5 Power Pins
SYMBOL
PIN
FUNCTION
VddLCPU,VddLAPIC
37,41,46
Power supply for CPU & IOAPIC, 2.5V or 3.3V.
Vdd48
5
Power supply for 48MHz output,3.3V.
VddA
24
Power supply for 3V_66 output, 3.3V.
VddP
15
Power supply for PCICLK, 3.3V.
VddR
Vdd
Vss
1
31
Power supply for REFX2, 3.3V.
Power for I2C CLK and DATA.
Circuit Ground.
2,8,12,19,25,30,36,
40,43
Publication Release Date:April. 2002
- 5 - Revision 1.0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W83196R-718B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VIA BUFFER CHIP (4 X DDR or 2 X DDR + 3 X SDRAM) |
| W83196S-14 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100 MHZ CLOCK FOR BX CHIPSET (2 CHIP) |
| W83196S-14/-14A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:100/133/150/160MHz Clock Gen.. with S.S.T.? |
| W83301 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ACPI-STR Controller |
| W83301DR-O | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ACPI-STR Controller |
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