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參數(shù)資料
| 型號： | W83196R-718 |
| 英文描述： | VIA Buffer Chip(4*DDR or 2*DDR + 3*SDRAM) |
| 中文描述： | 威盛緩沖芯片（4 * DDR或2 * 3 *的DDR SDRAM內(nèi)存） |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 731K |
| 代理商： | W83196R-718 |
W83194BR-250
4.1 Crystal I/O
SYMBOL
PIN
I/O
FUNCTION
Xin
3
IN
Crystal input with internal loading capacitors(36pF)
and feedback resistors.
Xout
4
OUT
Crystal output at 14.318MHz nominally with internal
loading capacitors(36pF).
4.2 CPU, AGP,PCI,IOAPIC Clock Outputs
SYMBOL
PIN
I/O
FUNCTION
CPUCLK_F , [1:3]
42,39,38,35
OUT
Low skew (< 250ps) clock outputs for host
frequencies such as CPU and Chipset.
CPUCLK_F is the free running pin and does not
affect by CPU_STOP#
CPU_STOP# when driven low.
Pin9 *Mode1=1, PCI_STOP# when driven low.
Pin9 *Mode1=0, RESET# output (4ms low active
pulse when Watch Dog time out)
Power Down mode when driven low.
Clock outputs synchronous with PCI clock and
powered by VddLAPIC.
3.3V 33MHz free running PCI clock during normal
operation. Latched input for Mode1* at initial power
up for pin34 selection.
*Mode1=1, pin 34 =CPU_STOP# when driven low.
*Mode1=0, pin 34 = RESET# output (4ms low active
pulse when Watch Dog time out)
Low skew (< 250ps) PCI clock outputs.
CPU_STOP#
PCI_STOP#/RESET$
34
33
IN
I/O
PD#
IOAPIC[0:1]
PCICLK_F/Mode1*
32
45,44
IN
OUT
9
I/O
PCICLK[1:8]
10,11,12,13,14
,16,17,18,20
23,26,27
21,22
OUT
AGP [0:2]
*FS[1:0]
OUT
IN
3.3V output clocks for the chipset.
H/W selecting the output frequency of CPU, AGP and
PCI clocks (Default=1).
Publication Release Date:April. 2002
- 4 - Revision 1.0
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W83196R-718B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VIA BUFFER CHIP (4 X DDR or 2 X DDR + 3 X SDRAM) |
| W83196S-14 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100 MHZ CLOCK FOR BX CHIPSET (2 CHIP) |
| W83196S-14/-14A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:100/133/150/160MHz Clock Gen.. with S.S.T.? |
| W83301 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ACPI-STR Controller |
| W83301DR-O | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ACPI-STR Controller |
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