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參數(shù)資料
| 型號： | W83196R-718 |
| 英文描述： | VIA Buffer Chip(4*DDR or 2*DDR + 3*SDRAM) |
| 中文描述： | 威盛緩沖芯片（4 * DDR或2 * 3 *的DDR SDRAM內(nèi)存） |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 731K |
| 代理商： | W83196R-718 |
W83194BR-250
1.0 GENERAL DESCRIPTION
The W83194BR-250 is a Clock Synthesizer for VIA Pro266 chipset. W83194BR-250 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, PCI, AGP, IOAPIC clocks frequency setting. All clocks are externally selectable
with smooth transitions.
The W83194BR-250 provides I
2
C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.
The W83194BR-250 provides stepless frequency programming by controlling the VCO freq. and the
clock output divisor ratio. Also the skew of CPU and AGP clock outputs are programmable. A watch
dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83194BR-250 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU
CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50
±
5%
duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns
slew rate.
2.0 PRODUCT FEATURES
4 CPU clocks
3 AGP for chipset and AGP clocks
9 PCI synchronous clocks.
Optional single or mixed supply:
(VddR = VddP= Vdd48 = VddA =Vdd = 3.3V, Vdd
LAPIC
=Vdd
LCPU
=2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
Smooth frequency switch with selections from 66.8 to
200
MHz
I
2
C 2-Wire serial interface and I
2
C read back
0.25% and 0.5% center type spread spectrum
Programmable registers to enable/stop each output and select modes
48 MHz for USB
24 MHz for super I/O
48-pin SSOP package
Publication Release Date:April. 2002
- 2 - Revision 1.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W83194BR-740 | Step-less Frequency SiS 733/735/740 Main Clock Gen. |
| W83194BR-P4X | Step-less VIA P4X/P4M Main Clock Gen. |
| W83194R-WE | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC |
| W83627SF | W83627F plus Smart Card Reader Interface. VID Control. GP I/O? |
| W83697UF | W83697F plus 2 Extra UART (total 4 UART) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W83196R-718B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VIA BUFFER CHIP (4 X DDR or 2 X DDR + 3 X SDRAM) |
| W83196S-14 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100 MHZ CLOCK FOR BX CHIPSET (2 CHIP) |
| W83196S-14/-14A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:100/133/150/160MHz Clock Gen.. with S.S.T.? |
| W83301 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ACPI-STR Controller |
| W83301DR-O | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ACPI-STR Controller |
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