參數(shù)資料
型號： W78M64VP120SBI
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA156
封裝： 13 X 22 MM, PLASTIC, BGA-156
文件頁數(shù)： 48/48頁
文件大?。?/td> 1548K
代理商： W78M64VP120SBI
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
During the Embedded Erase Algorithm, Data# polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The
system must provide an address within any of the sectors
selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on DQ7
is active for approximately 100 μs, then the device returns
to the read mode. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads DQ7 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, DQ7 may change asynchronously with
DQ6-DQ0 while Output Enable (OE#) is asserted low.
That is, the device may change from providing status
information to valid data on DQ7. Depending on when the
system samples the DQ7 output, it may read the status or
valid data. Even if the device has completed the program or
erase operation and DQ7 has valid data, the data outputs
on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00
appears on successive read cycles.
See the following for more information: Table 18, shows the
outputs for Data# Polling on DQ7. FIG: 7, shows the Data#
Polling algorithm; and FIG: 22, shows the Data# Polling
timing diagram.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the nal WE# pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address that is being
programmed or erased causes DQ6 to toggle. When the
operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 100μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erasesuspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6
toggles for approximately 1μs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program Algorithm
is complete.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-
asserted and reasserted to show the change in state.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the nal WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. But DQ2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 18 to compare outputs for DQ2
and DQ6.
Reading Toggle Bits DQ6/
DQ2
Whenever the system initially begins reading toggle bit status,
it must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the rst read.
After the second read, the system would compare the new
value of the toggle bit with the rst. If the toggle bit is not
toggling, the device has completed the program or erases
operation. The system can read array data on DQ7–DQ0
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