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| 型號： | W78M64VP120SBI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA156 |
| 封裝： | 13 X 22 MM, PLASTIC, BGA-156 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 1548K |
| 代理商： | W78M64VP120SBI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE 39 SECTOR PROTECTION COMMAND DEFINITIONS
Command
Cycles
Bus Cycles (Note 1-5)
First
Second
Third
Fouth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Lock
Register
Command Set Entry
3
555
AA
2AA
55
555
Program (6)
2
XXX
A0
XXX
DATA
Read (6)
1
00
RD
Command Set Exit (7, 8)
2
XXX
90
XXX
00
Password
Command Set Entry
3
555
AA
2AA
55
555
Password Program (9)
2
XXX
A0
PWAx
PWDx
Password Read (10)
4
00
PWD0
01
PWD 1
02
PWD 2
03
PWD 3
Password Unlock (10)
7
00
25
00
03
00
PWD 0
01
PWD 1
02
PWD 2
03
PWD 3
00
29
Command Set Exit (7, 8)
2
XXX
90
XXX
00
Global
Non-V
olatile
PPB Command Set Entry
3
555
AA
2AA
55
555
PPB Program (11, 12)
2
XXX
A0
SA
00
All PPB Erase (13)
2
XXX
80
00
30
PPB Status Read (12)
1
SA
RD (0)
PPB Command Set Exit (7, 8)
2
XXX
90
XXX
00
Global
V
olatile
Freeze
PPB Lock Cammand Set Entry
3
555
AA
2AA
55
555
PPB Lock Set (12)
2
XXX
A0
XXX
00
PPB Lock Command Set Exit (7, 8)
1
XXX
RD (0)
PPB Lock Command Set Exit (7, 8)
2
XXX
90
XXX
00
Volatile
DYB Command Set Entry
3
555
AA
2AA
55
555
DYB Set (11, 12)
2
XXX
A0
SA
00
DYB Clear (12)
2
XXX
A0
SA
01
DYB Status Read (12)
1
SA
RD (0)
DYB Command Set Exit (7, 8)
2
XXX
90
XXX
00
Legend
X = Don’t care
RD(0) = Read data.
SA = Sector Address. Address bits Amax–A16 uniquely select any sector.
Notes
1.
See Table 7.1 for description of bus operations.
2.
All values are in hexadecimal.
3.
All bus cycles are write cycles unless otherwise noted.
4.
Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5.
Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA
or PA required. (AMAX is the Highest Address pin.)
6.
All Lock Register bits are one-time programmable. Program state = “0” and the erase
state = “1.” The Persistent Protection Mode Lock Bit and the Password Protection
Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits
Program operation aborts and returns the device to read mode. Lock Register bits
that are reserved for future use default to “1’s.” The Lock Register is shipped out as
PWD = Password
PWDx = Password word0, word1, word2, and word3.
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,
PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit.
“FFFF’s” before Lock Register Bit program execution.
7.
The Exit command returns the device to reading the array.
8.
If any Command Set Entry command was written, an Exit command must be issued
to reset the device into read mode.
9.
For PWDx, only one portion of the password can be programmed per each “A0”
command.
10. Note that the password portion can be entered or read in any order as long as the
entire 64-bit password is entered or read.
11. If ACC = VHH, sector protection matches when ACC = VIH.
12. Protected State = “00h,” Unprotected State = “01h.”
13. The All PPB Erase command embeds programming of all PPB bits before erasure.
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