參數(shù)資料
型號(hào)： W78M64VP120SBI
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA156
封裝： 13 X 22 MM, PLASTIC, BGA-156
文件頁(yè)數(shù)： 47/48頁(yè)
文件大?。?/td> 1548K
代理商： W78M64VP120SBI
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
memory array. When the device exits the Autoselect mode,
the device reverts to Program Suspend mode, and is ready
for another valid operation. See Autoselect Section.
After the Program Resume command is written, the device
reverts to programming. The system can determine the
status of the program operation using the write operation
status bits, just as in the standard program operation. See
Write Operation Status Section for more information.
The system must write the Program Resume command
(address bits are “don't care”) to exit the Program Suspend
mode and continue the programming operation. Further
writes of the Program Resume command are ignored.
Another Program Suspend command can be written after
the device has resumed programming.
Accelerated Program
Accelerated single word programming and write buffer
programming operations are enabled through the WP#/
ACC pin. This method is faster than the standard program
command sequences.
NOTE
The accelerated program functions must not be used more
than 10 times per sector. If the system asserts VHH on this
input, the device automatically enters the aforementioned
Unlock Bypass mode and uses the higher voltage on the
input to reduce the time required for program operations.
The system can then use the Write Buffer Load command
sequence provided by the Unlock Bypass mode. Note that
if a “Write-to-Buffer-Abort Reset” is required while in Unlock
Bypass mode, the full 3-cycle RESET command sequence
must be used to reset the device. Removing VHH from the
ACC input, upon completion of the embedded program
operation, returns the device to normal operation.
Sectors must be unlocked prior to raising WP#/ACC
to VHH.
The WP#/ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
It is recommended that WP#/ACC apply VHH after
power-up sequence is completed. In addition, it is
recommended that WP#/ACC apply from VHH to
VIH/VIL before powering down VCC/VIO.
Unlock Bypass
This device features an Unlock Bypass mode to facilitate
shorter programming commands. Once the device enters
the Unlock Bypass mode, only two write cycles are required
to program data, instead of the normal four cycles.
This mode dispenses with the initial two unlock cycles
required in the standard program command sequence,
resulting in faster total programming time. The Command
Denitions shows the requirements for the unlock bypass
command sequences.
During the unlock bypass mode, only the Read, Program,
Write Buffer Programming, Write-to-Buffer-Abort Reset,
and Unlock Bypass Reset commands are valid. To exit the
unlock bypass mode, the system must issue the two-cycle
unlock bypass reset command sequence. The rst cycle
must contain the sector address and the data 90h. The
second cycle need only contain the data 00h. The sector
then returns to the read mode.
Write Operation Status
The device provides several bits to determine the status of
a program or erase operation. The following subsections
describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and
DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of
the final WE# pulse in the command sequence. Note
that the Data# Polling is valid only for the last word being
programmed in the write-buffer-page during Write Buffer
Programming. Reading Data# Polling status on any word
other than the last word to be programmed in the write-
buffer-page returns false status information.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed
to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to read
valid status information on DQ7. If a program address falls
within a protected sector, Data# polling on DQ7 is active,
then that sector returns to the read mode.
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