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參數(shù)資料
| 型號： | W78M32V100BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 32 FLASH 3.3V PROM, 100 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 21/54頁 |
| 文件大小： | 789K |
| 代理商： | W78M32V100BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specications without notice.
(ESN). The system can access the SecSi Sector region
by issuing the three-cycle Enter SecSi Sector command
sequence. The device continues to access the SecSi
Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi
Sector command sequence returns the device to normal
operation. The SecSi Sector is not accessible when the
device is executing an Embedded Program or embedded
Erase algorithm. Table 13 shows the address and data
requirements for both command sequences. See also
“SecSi (Secured Silicon) Sector Flash Memory Region”
for further information. Note that the ACC function and
unlock bypass modes are not available when the SecSi
Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system
is not required to provide further controls or timings. The
device automatically provides internally generated program
pulses and veries the programmed cell margin. Table 13
shows the address and data requirements for the program
command sequence. Note that the SecSi Sector, autoselect,
and CFI functions are unavailable when a [program/erase]
operation is in progress.
When the Embedded Program algorithm is complete, that
bank then returns to the read mode and addresses are no
longer latched. The system can determine the status of the
program operation by using DQ7, DQ6, or RY/BY#. Refer
to the Write Operation Status section for information on
these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the program operation. The program
command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from “0” back
to a “1.”
Attempting to do so may cause that bank to set
DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read
will show that the data is still “0.” Only erase operations can
convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
data to a bank faster than using the standard program
command sequence. The unlock bypass command
sequence is initiated by rst writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. That bank then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode.
The rst cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed
in the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
13 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid.
To exit the unlock bypass mode, the system must issue
the two-cycle unlock bypass reset command sequence.
(See Table 14)
The device offers accelerated program operations through
the WP#/ACC pin. When the system asserts VHH on the
WP# ACC pin, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
uses the higher voltage on the WP#/ACC pin to accelerate
the operation. Note that the WP#/ACC pin must not be at
VHH any operation other than accelerated programming,
or device damage may result. In addition, the WP#/ACC
pin must not be left oating or unconnected; inconsistent
behavior of the device may result.
Figure 6 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and Figure 16 for
timing diagrams.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
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| W78M32V100BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
| W78M32V100BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
| W78M32V120BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
| W78M32V120BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
| W78M32V120BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
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