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參數(shù)資料
| 型號： | W6694ACD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 567K |
| 代理商： | W6694ACD |
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Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-14-
Publication Release Date: May, 2001
Revision 1.03
L1DRR
Layer 1 D Channel Read Ready
1: A 8-bit data byte is received from D channel of ISDN Layer 1 interface (S or GCI). Software should read the
data byte from L1DDR register, and then write to USBDDW register. If USB D channel RFIFO is not already
enabled, this data will be lost.
0: Not ready for read.
L1DWR
Layer 1 D Channel Write Ready
1: A 8-bit data byte is sent to D channel of ISDN Layer 1 interface (S or GCI). Software can continue to read next
data byte from L1DDR register, and then write to USBDDW register. Initially this bit is automatically set to 1,
when the opening flag of a HDLC frame is received in USB D channel XFIFO, after being enabled.
0: Not ready for write.
CB1RR
Common B1 Channel Read Ready
1: A 8-bit data byte is received from logical B1 channel of ISDN Layer 1 interface (S or GCI), or from logical
channel 1 of PCM port. Software should read the data byte from CB1DR register, and then write to USBB1DW
register. If USB B1 channel RFIFO is not already enabled, this data will be lost.
0: Not ready for read.
CB1WR
Common B1 Channel Write Ready
1: A 8-bit data byte is sent to logical B1 channel of ISDN Layer 1 interface (S or GCI), or to logical channel 1 of
PCM port. Software can continue to read next data byte from USBB1DR register, and then write to CB1DW
register. Initially this bit is automatically set to 1, when the first USB B1 channel data byte is received in USB B1
channel XFIFO, after being enabled.
0: Not ready for write.
CB2RR
Common B2 Channel Read Ready
1: A 8-bit data byte is received from logical B2 channel of ISDN Layer 1 interface (S or GCI), or from logical
channel 2 of PCM port. Software should read the data byte from CB2DR register, and then write to USBB2DW
register. If USB B2 channel RFIFO is not already enabled, this data will be lost.
0: Not ready for read.
CB2WR
Common B2 Channel Write Ready
1: A 8-bit data byte is sent to logical B2 channel of ISDN Layer 1 interface (S or GCI), or to logical channel 2 of
PCM port. Software can continue to read next data byte from USBB2DR register, and then write to CB2DW
register. Initially this bit is automatically set to 1, when the first USB B2 channel data byte is received in USB B2
channel XFIFO, after being enabled.
0: Not ready for write.
7.2 USB
TABLE 7.2 USB ENDPOINTS
End
Point
Type
Direction*
Max. Packet Size
(Bytes)
Internal Buffer Type and Size
(Bytes)
0
Control
IN/OUT
8/8
8, single port x 2
1
Bulk
OUT
8
8, single port x 1
2
Bulk
IN
8
8, single port x 1
3
Interrupt
IN
5
5, single port x 1
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|---|---|
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