參數(shù)資料
型號： W6694ACD
廠商： WINBOND ELECTRONICS CORP
元件分類： 數(shù)字傳輸電路
英文描述： DATACOM, ISDN CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48
文件頁數(shù)： 34/42頁
文件大小： 567K
代理商： W6694ACD
Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-4-
Publication Release Date: May, 2001
Revision 1.03
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ........................................................................................................... 7
2. FEATURES................................................................................................................................... 7
3. PIN CONFIGURATION ................................................................................................................. 8
4. PIN DESCRIPTION....................................................................................................................... 9
5. SYSTEM DIAGRAM AND APPLICATIONS ............................................................................... 11
6. BLOCK DIAGRAM ..................................................................................................................... 12
7. FUNCTIONAL DESCRIPTIONS ................................................................................................. 13
7.1 Microcontroller .......................................................................................................................................................... 13
7.1.1 Special function register (SFR) ............................................................................................................................ 13
7.2 USB ........................................................................................................................................................................... 14
7.2.1 Control-IN Transactions (Endpoint 0).................................................................................................................. 15
7.2.2 Control-OUT Transactions (Endpoint 0).............................................................................................................. 17
7.2.3 Bulk-OUT Transaction (Endpoint 1).................................................................................................................... 18
7.2.4 Bulk-IN Transaction (Endpoint 2) ....................................................................................................................... 19
7.2.5 Interrupt-IN Transaction (Endpoint 3) ................................................................................................................. 19
7.2.6 Isochronous-OUT Transaction (Endpoint 4) ........................................................................................................ 19
7.2.7 Isochronous-IN Transaction (Endpoint 5) ............................................................................................................ 20
7.2.8 Suspend and Resume ........................................................................................................................................... 21
7.3 EEPROM Configuration............................................................................................................................................. 23
7.3.1 EEPROM wire connection ................................................................................................................................... 23
7.3.2 EEPROM Contents.............................................................................................................................................. 23
8. REGISTER DESCRIPTIONS ...................................................................................................... 24
8.1 Interrupt Registers...................................................................................................................................................... 24
8.1.1 Interrupt Status Register
ISTA Read_clear ..................................................................................................... 24
8.1.2 Layer 1 Command/Indication Register
CIR Read ............................................................................................. 24
8.1.3 PIO Input Change Register
PICR Read_clear ................................................................................................. 25
8.1.4 Monitor Channel Interrupt Status
MOIR Read_clear ....................................................................................... 25
8.2 Chip and FIFO Control Registers ............................................................................................................................... 25
8.2.1 Interrupt Mask Register
IMASK Read/Write Address 00h .............................................................................. 25
8.2.2 Command Register 1
CMDR1 Write Address 01h ........................................................................................ 26
8.2.3 Command Register 2
CMDR2 Write Address 02h ........................................................................................ 27
8.2.4 Control Register
CTL Read/Write Address 03h ............................................................................................ 27
8.2.5 Layer 1 Command/Indication Register
CIX Read/Write Address 04h ............................................................... 28
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