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參數(shù)資料
| 型號(hào)： | W6694ACD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 18/42頁 |
| 文件大?。?/td> | 567K |
| 代理商： | W6694ACD |
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Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-25-
Publication Release Date: May, 2001
Revision 1.03
Note: If S/T layer 1 function is disabled and GCI bus is enabled (GE=1 in GCR register), CIR register is used to receive layer
1 indication code from U transceiver. In this case, the supported indication codes are :
Indication
Symbol
Code
Descriptions
Deactivation confirmation
DC
1111
Idle code on GCI interface
Power up indication
PU
0111
U transceiver power up
8.1.3 PIO Input Change Register
PICR
Read_clear
Value after reset: 00h
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
P7-0
Indicator of IO Pin Input Status
0: This IO pin is either output pin, or did not change input value.
1: This IO pin changed value.
8.1.4 Monitor Channel Interrupt Status
MOIR
Read_clear
Value after reset: 00h
7
6
5
4
3
2
1
0
MDR
MER
MDA
MAB
MDR
Monitor Channel Data Receive
MER
Monitor Channel End of Reception
MDA
Monitor Channel Data Acknowledged
MAB
Monitor Channel Data Abort
NOTE : Registers in sections 8.2 to 8.5 are written/read by Bulk-OUT/Bulk-IN transactions.
8.2 Chip and FIFO Control Registers
8.2.1 Interrupt Mask Register
IMASK
Read/Write
Address 00h
Value after reset: F0h
7
6
5
4
3
2
1
0
ICC
MOC
PIOIC
EPAC
0
Setting 1 to each bits masks the corresponding interrupt sources in ISTA register.
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