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參數(shù)資料
| 型號： | W6694ACD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 20/42頁 |
| 文件大?。?/td> | 567K |
| 代理商： | W6694ACD |
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Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-27-
Publication Release Date: May, 2001
Revision 1.03
Setting this bit activates the remote loop back function. The received 2B channels from the S/T interface are looped
to the transmitted 2B channels of S/T interface. The D channel is not looped in this loop back function.
This bit remains set, until cleared by software reset (SRST).
8.2.3 Command Register 2
CMDR2
Write
Address 02h
Value after reset: 00h
Bits in this register act similar to that of CMDR1 register, except that the effect is on B1 or B2 channel XFIFO/RFIFO,
instead of on D channel XFIFO/RFIFO.
7
6
5
4
3
2
1
0
B1XRST
B1RRST
B1XEN
B1REN
B2XRST
B2RRST
B2XEN
B2REN
B1XRST
B1 Channel Transmitter Reset
B1RRST
B1 Channel Receiver Reset
B1XEN
B1 Channel Transmit FIFO Enable
B1REN
B1 Channel Receive FIFO Enable
B2XRST
B2 Channel Transmitter Reset
B2RRST
B2 Channel Receiver Reset
B2XEN
B2 Channel Transmit FIFO Enable
B2REN
B2 Channel Receive FIFO Enable
8.2.4 Control Register
CTL
Read/Write
Address 03h
Value after reset : 00H
7
6
5
4
3
2
1
0
BAM
0
OPS1
OPS0
BAM
B Channel Auto Mode
This mode let hardware automatically enable B1 or B2 channel transmit FIFO (XFIFO), whenever there is any error
occurred for B channel XFIFO. No B channel XFIFO error status is reported to USB host. Writing 0 to this bit
disable auto mode.
OPS1-0 Output Phase Delay Compensation Select1-0
These two bits select the output phase delay compensation.
OPS1
OPS0
Effect
0
No output phase delay compensation
0
1
Output phase delay compensation 260ns
1
0
Output phase delay compensation 520 ns
1
Output phase delay compensation 1040 ns
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相關代理商/技術參數(shù) |
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|---|---|
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