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參數(shù)資料
| 型號(hào)： | W3HG64M64EEU403D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 207K |
| 代理商： | W3HG64M64EEU403D4SG |
W3HG64M64EEU-D4
October 2005
Rev. 0
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
AC OPERATING CONDITIONS
≤TCASE≤+85°C; VCC = +1.8V ±0.1V
Clock
AC Characteristics
Symbol
806
665
534
403
Units
Notes
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Clock cycle time
CL = 6
tCK (6)
TBD
CL = 5
tCK (5)
TBD
3,000 8,000
-
ps
16,25
CL = 4
tCK (4)
TBD
3, 750 8,000 3,750 8,000 5,000 8,000
ps
16,25
CL = 3
tCK (3)
TBD
5,000 8,000 5,000 8,000 5,000 8,000
ps
16,25
CK low-level width
tCL
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
19
Half clock period
tHP
TBD
MIN
(
tCH,tCL)
MIN
(
tCH,tCL)
MIN
(
tCH,tCL)
ps
20
Clock jitter
tJIT
TBD
ps
18
Data
DQ output access time from CK/CK#
tAC
TBD
-450
-500 +500 -600 +600
ps
Data-out high-impedance window from CK/CK#
tHZ
TBD
tAC
(MAX)
tAC
(MAX)
tAC
(MAX)
ps
8, 9
Data-out low-impedance window from CK/CK#
tLZ
TBD
tAC (MIN) tAC
(MAX)
tAC (MIN) tAC
(MAX)
tAC (MIN) tAC
(MAX)
ps
8, 10
DQ and DM input setup time relative to DQS
tDSa
TBD
300
350
400
ps
7, 15,
22
DQ and DM input hold time relative to DQS
tDHa
TBD
300
350
400
ps
7, 15,
22
DQ and DM input setup time relative to DQS
tDSb
TBD
100
150
ps
7, 15,
22
DQ and DM input hold time relative to DQS
tDHb
TBD
175
225
275
ps
7, 15,
22
DQ and DM input pulse width (for each input)
tDIPW
TBD
0.35
tCK
Data hold skew factor
tQHS
TBD
340
400
450
ps
DQ–DQS hold, DQS to rst DQ to go nonvalid, per access
tQH
TBD
tHP-tQHS
ps
15, 17
Data valid output window (DVW)
tDVW
TBD
tQH
-
tDQSQ
tQH
-
tDQSQ
tQH
-
tDQSQ
ns
15, 17
Note:
AC specication is based on
MICRON components. Other DRAM manufactures specications may be different.
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