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參數(shù)資料
| 型號(hào)： | W3HG64M64EEU403D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 207K |
| 代理商： | W3HG64M64EEU403D4SG |
W3HG64M64EEU-D4
October 2005
Rev. 0
ADVANCED*
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
Notes:
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specications and device
operation are guaranteed for the full voltage range specied.
3. Outputs measured with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test
environment and parameter specications are guaranteed for the specied AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH
(AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as
specied.
5. The AC and DC input level specications are as dened in the SSTL_18 standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
6. Command/Address minimum input slew rate is at 1.0V/ns. Command/Address input
timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated
using tISb and the Setup and Hold Time Derating Values table. tIS timing (tISb)
is referenced from VIH(AC) for a rising signal and VIL(DC) for a falling signal. The
timing table also lists the tISb and tIHb values for a 1.0V/ns slew rate; these are the
“base” values.
7. Data minimum input slew rate is at 1.0V/ns. Data input timing must be derated if
the slew rate is not 1.0V/ns. This is easily accommodated if the timing is referenced
from the logic trip points. tDS timing (tDSb) is referenced from VIH (AC) for a rising
signal and VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH(DC) for
a rising signal and VIL(DC) for a falling signal. The timing table lists the tDSb and tDHb
values for a 1.0V/ns slew rate. If the DQS/DQS# differential strobe feature is not
enabled, timing is no longer referenced to the crosspoint of DQS/DQS#. Data timing
is now referenced to VREF, provided the DQS slew rate is not less than 1.0V/ns.
If the DQS slew rate is less than 1.0V/ns, then data timing is now referenced to
VIH(AC) for a rising DQS and VIL(DC) for a falling DQS.
8. tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specic voltage level, but
specify when the device output is no longer driving (tHZ) or begins driving (tLZ).
9. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail
over tDQSCK (MAX) + tRPST (MAX) condition.
10. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition
11. The intent of the Don’t Care state after completion of the postamble is the DQS-
driven signal should either be high, low or High-Z and that any signal transition
within the input switching region must follow valid input requirements. That is if DQS
transitions high (above VIHDC(min) then it must not transition low (below VIH(DC)
prior to tDQSH(min).
12. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
14. The refresh period is 64ms. This equates to an average refresh rate of 7.8125μs.
How-ever, a REFRESH command must be asserted at least once every 70.3μs or
t
RFC (MAX). To ensure all rows of all banks are properly refreshed, 8192 REFRESH
commands must be issued every 64ms.
15. Each byte lane has a corresponding DQS.
16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2 V/ns if measured differentially).
17. The data valid window is derived by achieving other specications - tHP. (tCK/2),
t
DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct
proportion to the clock duty cycle and a practical data valid window can be derived.
18. tJIT specication is currently TBD.
19. MIN(tCL, tCH) refers to the smaller of the actual clock low time and the actual clock
high time as provided to the device (i.e. This value can be greater than the minimum
specication limits for tCL and tCH). For example, tCL and tCH are = 50 percent of
the period, less the half period jitter [tJIT(HP)] of the clock source, and less the half
period jitter due to cross talk [tJIT(cross talk)] into the clock traces.
20. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs.
21. READs and WRITEs with auto precharge are allowed to be issued before tRAS
(MIN) is satised since tRAS lockout feature is supported in DDR2 SDRAM devices.
22. VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb SDRAM data sheet for
more detail.
23. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer,
round to the next highest integer. tCK refers to the application clock period;
AC Operation Condition Notes: nWR refers to the tWR parameter stored in the
MR[11,10,9]. Example: For -533 Mb/s at tCK = 3.75 ns with tWR programmed to
four clocks. tDAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks.
24. The minimum READ to internal PRECHARGE time. This parameter is only
applicable when tRTP/(2*tCK) > 1. If tRTP/(2*tCK) ≤ 1, then equation AL + BL/2
applies. Notwithstanding, tRAS (MIN) has to be satised as well. The DDR2 SDRAM
device will automatically delay the internal PRECHARGE command until tRAS (MIN)
has been satised.
25. Operating frequency is only allowed to change during self refresh mode, precharge
power-down mode, and system reset condition.
26. ODT turn-on time tAON (MIN) is when the device leaves high impedance and
ODT resistance begins to turn on. ODT turn-on time tAON (MAX) is when the ODT
resistance is fully on. Both are measured from tAOND.
27. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance.
ODT turn off time tAOF (MAX) is when the bus is in high impedance. Both are
measured from tAOFD.
28. This parameter has a two clock minimum requirement at any tCK.
29. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is
guaranteed prior to CK, CK# being removed in a system RESET condition.
30. tISXR is equal to tIS and is used for CKE setup time during self refresh exit.
31. No more than 4 bank ACTIVE commands may be issued in a given tFAW(min)
period. tRRD(min) restriction still applies. The tFAW(min) parameter applies to all 8
bank DDR2 devices, regardless of the number of banks already open or closed.
32. tRPA timing applies when the PRECHARGE(ALL) command is issued, regardless
of the number of banks already open or closed. If a single-bank PRECHARGE
command is issued, tRP timing applies. tRPA(MIN) applies to all 8-bank DDR2
devices.
33. Value is minimum pulse width, not the number of clock registrations.
34. Applicable to Read cycles only. Write cycles generally require additional time due to
Write recovery time (tWR) during auto precharge.
35. tCKE (MIN) of 3 clocks means CKE must be registered on three consecutive
positive clock edges. CKE must remain at the valid input level the entire time it takes
to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
36. This parameter is not referenced to a specic voltage level, but specied when the
device output is no longer driving (tRPST) or beginning to drive (tRPRE).
37. When DQS is used single-ended, the minimum limit is reduced by 100ps.
Output
(VOUT)
Reference
Point
25Ω
VTT = VCCQ/2
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