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參數(shù)資料
| 型號： | W3HG64M64EEU403D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 207K |
| 代理商： | W3HG64M64EEU403D4SG |
W3HG64M64EEU-D4
October 2005
Rev. 0
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
AC OPERATING CONDITIONS (continued)
≤TCASE≤+85°C; VCC = +1.8V ±0.1V
Data
Strobe
AC Characteristics
Symbol
806
665
534
403
Units
Notes
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
DQS input high pulse width
tDQSH
TBD
0.35
tCK
DQS input low pulse width
tDQSL
TBD
0.35
tCK
DQS output access time from CK/CK#
tDQSCK
TBD
-400 +400 -450 +450 -500 +500
ps
DQS falling edge to CK rising – setup time
tDSS
TBD
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
TBD
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
TBD
240
300
350
ps
15, 17
DQS read preamble
tRPRE
TBD
0.9
1.1
0.9
1.1
0.9
1.1
tCK
36
DQS read postamble
tRPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
36
DQS write preamble setup time
tWPRES
TBD
0
ps
12, 13,
37
DQS write preamble
tWPRE
TBD
0.35
0.25
tCK
DQS write postamble
tWPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
11
Write command to rst DQS latching transition
tDQSS
TBD
WL
- 0.25
WL+
0.25
WL -
0.25
WL+
0.25
WL -
0.25
WL+
0.25
tCK
Command
and
Address
Address and control input pulse width for each input
tIPW
TBD
0.6
tCK
Address and control input setup time
tISa
TBD
400
500
600
ps
6, 22
Address and control input hold time
tIHa
TBD
400
500
600
ps
6, 22
Address and control input setup time
tISb
TBD
200
250
350
ps
6, 22
Address and control input hold time
tIHb
TBD
275
375
475
6, 22
CAS# to CAS# command delay
tCCD
TBD
222tCK
ACTIVE to ACTIVE (same bank) command
tRC
TBD
55
ns
34
ACTIVE bank a to ACTIVE bank command
tRRD
TBD
7.5
ns
28
ACTIVE to READ or WRITE delay
tRCD
TBD
15
ns
Four Bank Activate period
tFAW
TBD
37.5
ns
31
ACTIVE to PRECHARGE command
tRAS
TBD
40
70,000
40
70,000
40
70,000
ns
21, 34
Internal READ to precharge command delay
tRTP
TBD
7.5
ns
24, 28
Write recovery time
tWR
TBD
15
ns
28
Auto precharge write recovery + precharge time
tDAL
TBD
tWR +
tRP
tWR +
tRP
tWR +
tRP
ns
23
Internal WRITE to READ command delay
tWTR
TBD
10
7.5
10
ns
28
PRECHARGE command period
tRP
TBD
15
ns
32
PRECHARGE ALL command period
tRPA
TBD
tRP + tRP
tRP +
tRP
tRP +
tRP
ns
32
LOAD MODE command cycle time
tMRD
TBD
222tCK
CKE low to CK,CK# uncertainty
tDELAY
TBD
tIS + tCK
+
tIH
tIS +
tCK +
tIH
tIS +
tCK +
tIH
ns
29
Note:
AC specication is based on
MICRON components. Other DRAM manufactures specications may be different.
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