參數(shù)資料
型號(hào)： W3H32M64EA-667SBC
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 32M X 64 DDR DRAM, PBGA208
封裝： 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 3/28頁(yè)
文件大?。?/td> 1057K
代理商： W3H32M64EA-667SBC
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2010 2010 White Electronic Designs Corp. All rights reserved
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
W3H32M64EA-XSBX
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
on die termination (ODT) (RTT), posted AL, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specied time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecied operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
DLL
Posted CAS# R
TT
Out
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended mode
register (Ex)
Address bus
97
6
5
4
3
82
1
0
A10
A12
BA0
BA1
10
11
12
n
0
14
E1
0
1
Output Drive Strength
Full
Reduced
Posted CAS# Additive Latency (AL)
3
0
1
2
3
4
5
6
Reserved
E3
0
1
0
1
0
1
0
1
E4
0
1
0
1
E5
0
1
0
1
DLL Enable
Enable (normal)
Disable (test/debug)
E0
15
E11
0
1
RDQS Enable
No
Yes
OCD Program
An
2
ODS
R
TT
DQS#
E10
0
1
DQS# Enable
Enable
Disable
RDQS
R
TT (Nominal)
R
TT disabled
75Ω
150Ω
50Ω
E2
0
1
0
1
E6
0
1
0
1
Outputs
Enabled
Disabled
E12
0
1
0
1
Mode Register Set
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
E15
0
1
E14
MRS
BA2
1
16
0
OCD Operation
4
OCD exit
Reserved
Enable OCD defaults
E7
0
1
0
1
E8
0
1
0
1
E9
0
1
Notes:
1.
E16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be programmed to “0.”
2.
Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved for future use and must be
programmed to “0.”
3.
Not all listed AL options are supported.
4.
During initialization of the OCD operation, all three bits must be set to “1” for the OCD default state, then set to “0” before
initialization is nished.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3H32M64E-ES 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H32M64E-ESC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H32M64E-ESI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H32M64E-ESM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H32M64E-SB 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
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