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| 型號(hào)： | W3H128M72E-667SBM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 1.25 ns, PBGA208 |
| 封裝： | 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁(yè)數(shù)： | 18/32頁(yè) |
| 文件大?。?/td> | 988K |
| 代理商： | W3H128M72E-667SBM |
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W3H128M72E-XSBX
25
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC TIMING PARAMETERS
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Min
Max
Min
Max
Min
Max
Clock
Clock cycle time
CL=6
tCK(6)
3,000
8,000
CL=5
tCK(5)
3,000
8,000
3,750
8,000
5,000
8,000
ps
CL=4
tCK(6)
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.48
0.52
0.48
0.52
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
MIN (tCH, tCL)
MIN (tCH, tCL)ps
Clock
(absolute)
Absolute tCK
tCKabs
tCKAVG
(MIN)
+ tJITPER
(MIN)
tCKAVG
(MAX)
+ tJITPER
(MAX)
tCKAVG
(MIN)
+ tJITPER
(MIN)
tCKAVG
(MAX)
+ tJITPER
(MAX)
tCKAVG
(MIN)
+ tJITPER
(MIN)
tCKAVG
(MAX)
+ tJITPER
(MAX)
ps
Absolute CK high-level width
tCHabs
tCKAVG
(MIN)
* tCHAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCHAVG
(MAX)
+ tJITDTY
(MAX)
tCKAVG
(MIN)
* tCHAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCHAVG
(MAX)
+ tJITDTY
(MAX)
tCKAVG
(MIN)
* tCHAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
* tCHAVG
(MAX)
+ tJITDTY
(MAX)
ps
Absolute CK low-level width
tCLabs
tCKAVG
(MIN)
*
tCLAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCLAVG
(MAX)
+ tJITDTY
(MAX)
tCKAVG
(MIN)
*
tCLAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCLAVG
(MAX)
+ tJITDTY
(MAX)
tCKAVG
(MIN)
*
tCLAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCLAVG
(MAX)
+ tJITDTY
(MAX)
ps
Clock
Jitter
Clock jitter - period
tJITPER
-125
125
-125
125
-125
125
ps
Clock jitter - half period
tJITDUTY
-125
125
-125
125
-125
125
ps
Clock jitter - cycle to cycle
tJITCC
250
ps
Cumulative jitter error, 2 cycles
tERR2per
-175
175
-175
175
-175
175
ps
Cumulative jitter error, 3 cycles
tERR3per
-225
225
-225
225
-225
225
ps
Cumulative jitter error, 4 cycles
tERR4per
-250
250
-250
250
-250
250
ps
Cumulative jitter error, 5 cycles
tERR5per
-250
250
-250
250
-250
250
ps
Cumulative jitter error, 6-10 cycles
tERR6-10per
-350
350
-350
350
-350
350
ps
Cumulative jitter error, 11-50 cycles
tERR11-50per
-450
450
-450
450
-450
450
ps
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