參數(shù)資料
型號: W3H128M72E-667SBM
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM, 1.25 ns, PBGA208
封裝: 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁數(shù): 1/32頁
文件大小: 988K
代理商: W3H128M72E-667SBM
W3H128M72E-XSBX
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667, 533, 400
Package:
208 Plastic Ball Grid Array (PBGA), 16 x 22mm
1.0mm pitch
Core Supply Voltage = 1.8V ± 0.1V
I/O Supply Voltage = 1.8V ± 0.1V - (SSTL_18
compatible)
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 4, 5 or 6
CK/CK# Termination options available
0 ohm, 20 ohm
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Commercial, Industrial and Military Temperature
Ranges
Organized as 128M x 72
Weight: W3H128M72E-XSBX - 4 grams max
BENEFITS
56% space savings vs. FBGA
Reduced part count
50% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Thinner "NB" version of part is under development.
Only difference in the part will be the thickness is
3.97mm (0.156) max, a reduction of .68mm (.027)
* This product is subject to change without notice.
Area
5 x 161mm2 = 805mm2
352mm2
56%
5 x 84 balls = 420 balls
208 Balls
50%
S
A
V
I
N
G
S
I/O
Count
W3H128M72E-XSBX
CSP Approach (mm)
84
FBGA
11.5
14.0
22
16
84
FBGA
11.5
84
FBGA
11.5
84
FBGA
11.5
84
FBGA
11.5
FIGURE 1 – DENSITY COMPARISONS
White Electronic Designs
W3H128M72E-XSBX
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