參數(shù)資料
型號: W3H128M72E-667SBM
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM, 1.25 ns, PBGA208
封裝: 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁數(shù): 10/32頁
文件大?。?/td> 988K
代理商: W3H128M72E-667SBM
W3H128M72E-XSBX
18
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
READ COMMAND
The READ command is used to initiate a burst read access
to an active row. The value on the BA2–BA0 inputs selects
the bank, and the address provided on inputs A0–i (where
i = A9) selects the starting column location. The value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed
will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
READ OPERATION
READ bursts are initiated with a READ command. The
starting column and bank addresses are provided with the
READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is automatically precharged at the
completion of the burst. If auto precharge is disabled, the
row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the
starting column address will be available READ latency
(RL) clocks later. RL is dened as the sum of AL and CL;
RL = AL + CL. The value for AL and CL are programmable
via the MR and EMR commands, respectively. Each
subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next
crossing of CK and CK#).
DQS/DQS# is driven by the DDR2 SDRAM along with
output data. The initial LOW state on DQS and HIGH state
on DQS# is known as the read preamble (tRPRE). The LOW
state on DQS and HIGH state on DQS# coincident with
the last data-out element is known as the read postamble
(tRPST).
Upon completion of a burst, assuming no other commands
have been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with
data from a subsequent READ command to provide a
continuous ow of data. The rst data element from the
new burst follows the last element of a completed burst.
The new READ command should be issued x cycles after
the rst READ command, where x equals BL / 2 cycles.
FIGURE 11 – READ COMMAND
DON’T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Col
Bank
ADDRESS
BANK ADDRESS
AUTO PRECHARGE
ENABLE
DISABLE
A10
相關PDF資料
PDF描述
WF128K32N-150HC5A 512K X 8 FLASH 5V PROM MODULE, 150 ns, CPGA66
WS128K32NV-25H1M 128K X 32 MULTI DEVICE SRAM MODULE, 25 ns, CPGA66
WE128K32-200G4Q 128K X 32 EEPROM 5V MODULE, 200 ns, CQMA68
WE128K32-250G4M 128K X 32 EEPROM 5V MODULE, 250 ns, CQMA68
WF512K32F-70H1C5 512K X 32 FLASH 5V PROM MODULE, 70 ns, CPGA66
相關代理商/技術參數(shù)
參數(shù)描述
W3H13C1048AT 制造商:AVX 制造商全稱:AVX Corporation 功能描述:High Current Feedthry Capacitors
W3H13C1048AT1A 功能描述:饋通電容器 25volt 0.1uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體:
W3H13C1048AT1F 功能描述:饋通電容器 25volt 0.1uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體:
W3H15C1038AT 制造商:AVX 制造商全稱:AVX Corporation 功能描述:High Current Feedthry Capacitors
W3H15C1038AT1A 功能描述:饋通電容器 50volt .01uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體: