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參數(shù)資料
| 型號(hào)： | W3EG6433S262D3 |
| 英文描述： | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| 中文描述： | 256MB的- 2x16Mx64 DDR內(nèi)存緩沖 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | W3EG6433S262D3 |
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-D3
-JD3
November 2005
Rev. 2
PRELIMINARY
9.
10.
Slew Rate is measured between V
OH
(ac) and V
OL
(ac).
Min (t
CL
, t
CH
) refers to the smaller of the actual clock low time and
the actual clock high time as provided to the device (i.e. this value
can be greater than the minimum specification limits for t
CL
and
t
CH
. For example, t
CL
and t
CH
are = 50% of the period, less the half
period jitter (t
JIT
(HP)) of the clock source, and less the half period
jitter due to crosstalk (t
JIT
(crosstalk)) into the clock traces.
QH
= t
HP
- t
QHS
, where:
t
HP =
minimum half clock period for any given cycle and is defined
by clock high or clock low t
CH
, t
CL
). t
QHS
accounts for 1) The pulse
duration distortion of on-chip clock circuits; and 2) The worst case
push-out of DQS on one transition followed by the worst case
pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
DQSQ
Consists of data pin skew and output pattern effects and p-channel
to n-channel variation of the output
drivers for any given cycle.
DAL
= (t
WR
/t
CK
) + (t
RP
/t
CK
)
For each of the terms above, if not already an integer, round to
the next highest integer. Example: For DDR266 at CL=2.5 and
t
CK
=7.5ns t
DAL
= (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) t
DAL
=
5 clocks
11.
12.
13.
Notes
1.
t
HZ
and t
LZ
transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output in no
longer driving (HZ), or begins driving (LZ).
The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
The specific requirement is that DQS be valid (HIGH, LOW, or at
some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate
specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from High- Z to logic
LOW. If a previous write was in progress, DQS could be HIGH,
LOW, or transitioning from HIGH to LOW at this time, depending
on t
DQSS.
A maximum of eight AUTO REFRESH commands can be posted
to any given DDR SDRAM device.
For command/address input slew rate ≥ 1.0 V/ns.
For command/address input slew rate ≥ 0.5 V/ns and > 1.0 V/ns
For CK & CK# slew rate ≥ 1.0 V/ns.
These parameters guarantee device timing, but they are not
necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
2.
3.
4.
5.
6.
7.
8.
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