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參數(shù)資料
| 型號： | W3EG6433S262D3 |
| 英文描述： | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| 中文描述： | 256MB的- 2x16Mx64 DDR內(nèi)存緩沖 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 246K |
| 代理商： | W3EG6433S262D3 |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-D3
-JD3
November 2005
Rev. 2
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
335
(DDR333@CL=2.5
)
(DDR266@CL=2.0)
AC Characteristics
262
263
(DDR266@CL=2.0)
265
(DDR266@CL=2.5)
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Symbol
t
RC
t
RFC
t
RAS
t
RCD
t
RP
t
RRD
t
WR
t
WTD
t
CCD
t
CK
Min
60
72
42
18
18
12
15
1
1
7.5
6
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.8
0.8
Max
Min
60
75
45
15
15
15
15
1
1
7.5
7.5
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
Max
Min
65
75
45
20
20
15
15
1
1
7.5
7.5
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
Max
Min
65
75
45
20
20
15
15
1
1
10
7.5
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
ns
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
t
CK
ns
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
V/ns
V/ns
Notes
70K
120K
120K
120K
CL=2.0
CL=2.5
12
12
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to output data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from Ck rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time (fast)
Address and Control Input hold time (fast)
Address and Control Input setup time (slow)
Address and Control Input setup time (slow)
Data-out high impedence time from CK/CK
Data-out high impedence time from CK/CK
Input Slew Rate (for input only pins)
Input Slew Rate (for I/O pins)
t
CH
t
CL
t
DQSCK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPRE
t
DSS
t
DSH
t
DQSH
t
DQSL
t
DSC
t
IS
t
IH
t
IS
t
IH
t
HZ
t
LZ
t
SL(I)
t
SL(IO)
12
3
1.1
1.1
1.1
1.1
i,5.7~9
i,5.7~9
i,6~9
i,6~9
1
1
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
+0.75
+0.75
-0.7
0.5
0.5
-0.75
0.5
0.5
-0.75
0.5
0.5
-0.75
0.5
0.5
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| W3EG6433S263D3 | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
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| W3EG6433S335D3 | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S335JD3 | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG6433S263D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S263JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S265AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6433S265BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6433S265D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
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