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參數(shù)資料
| 型號： | W3EG6433S262D3 |
| 英文描述： | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| 中文描述： | 256MB的- 2x16Mx64 DDR內(nèi)存緩沖 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 246K |
| 代理商： | W3EG6433S262D3 |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-D3
-JD3
November 2005
Rev. 2
PRELIMINARY
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge;
t
=t
(MIN); t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
=t
(MIN);
t
=t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
DDR333@CL=2.5
Max
680
DDR266@CL=2
Max
640
DDR266@CL=2/2.5
Max
640
Units
mA
Operating Current
I
DD1
880
800
800
mA
Precharge Power-
Down Standby
Current
Idle Standby Current
I
DD2P
24
24
24
rnA
I
DD2F
CS# = High; All device banks idle;
t
=t
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
=t
(MAX); t
=t
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
t
RC
= t
RC
(MIN)
200
180
180
mA
Active Power-Down
Standby Current
Active Standby
Current
I
DD3P
240
200
200
mA
I
DD3N
360
320
320
mA
Operating Current
I
DD4R
1,120
960
960
mA
Operating Current
I
DD4W
1,160
1,000
1,000
rnA
Auto Refresh
Current
Self Refresh Current
Operating Current
I
DD5
1,320
1,240
1,240
mA
I
DD6
I
DD7A
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN); t
=t
(MIN); Address and
control inputs change only during
Active Read or Write commands.
16
16
16
mA
mA
2,400
2,000
2,000
NOTES:
Module I
DD
was calculated on the basis of component I
DD
and can be different measured according to dq hearing cap.
DD
specification is based on
SAMSUNG
components. Other DRAM manufactures specification may be different.
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