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參數(shù)資料
| 型號(hào)： | W26L11H-70LL |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 134K |
| 代理商： | W26L11H-70LL |
Preliminary W26L11
Publication Release Date: October 1999
- 7 -
Revision A1
Timing Waveforms, continued
Write Cycle 2
(OE = VIL Fixed)
Address
WE
D
T
(2)
(3)
T
WC
AW
WP
OW
WHZ (1, 4)
DW
DH
OH
AS
OUT
IN
CS
T
CW
WR
UB/LB
TBW
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured
±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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