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參數(shù)資料
| 型號： | W25Q80VZPI |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 8 SPI BUS SERIAL EEPROM, DSO8 |
| 封裝： | 6 X 5 MM, WSON-8 |
| 文件頁數(shù)： | 5/60頁 |
| 文件大?。?/td> | 1276K |
| 代理商： | W25Q80VZPI |
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W25Q80, W25Q16, W25Q32
Publication Release Date: June 20, 2007
- 13 -
Advanced - Revision A5
10.1.6 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1 SRP0
/WP
Status
Register
Description
0
X
Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and can not
be written to.
0
1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
1
0
X
Power Supply
Lock-Down
Status Register is protected and can not be written to again
until the next power-down, power-up cycle.
(1)
1
X
One Time
Program
Status Register is permanently protected and can not be
written to.
Note:
1. When SRP1, SRP0 = (1,0), a power-down, power-up cycle will change SRP1, SRP0 to (0,0) state.
10.1.7 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad
operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When
the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled.
WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the
/WP or /HOLD pins are tied directly to the power supply or ground.
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