- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202121 > W25Q80BVSNAP (WINBOND ELECTRONICS CORP) 8M X 1 SPI BUS SERIAL EEPROM, PDSO8 PDF資料下載
參數(shù)資料
| 型號： | W25Q80BVSNAP |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 74/75頁 |
| 文件大小： | 1055K |
| 代理商： | W25Q80BVSNAP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁當(dāng)前第74頁第75頁
W25Q80BV
- 8 -
6.1 Package Types
W25Q80BV is offered in an 8-pin plastic 150-mil or 208-mil width SOIC (package code SN & SS) and
6x5-mm WSON (package code ZP) as shown in figure 1a and 1b respectively. The W25Q80BV is also
offered in a 8-pin plastic 300-mil width PDIP (package code DA) as shown in figure 1c. Package
diagrams and dimensions are illustrated at the end of this datasheet.
6.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted.
The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 38). If
needed a pull-up resister on /CS can be used to accomplish this.
6.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q80BV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read
data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
6.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be
hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,
the /WP pin function is not available since this pin is used for IO2. See figure 1a-c for the pin
configuration of Quad I/O operation.
6.5 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
used for IO3. See figure 1a-c for the pin configuration of Quad I/O operation.
6.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WV3EG128M72EFSR262D3MG | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W7NCF08GH10CS4FM1G | FLASH 3.3V PROM MODULE, XMA50 |
| W7NCF08GH10CSA5DM1G | FLASH 3.3V PROM MODULE, XMA50 |
| W7NCF08GH10IS8BM1G | FLASH 3.3V PROM MODULE, XMA50 |
| W7NCF08GH10ISA4HM1G | FLASH 3.3V PROM MODULE, XMA50 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q80BVSNIG | 功能描述:IC SPI FLASH 8MBIT 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標(biāo)準(zhǔn)包裝:2,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:256K (32K x 8) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:28-TSSOP（0.465"，11.8mm 寬） 供應(yīng)商設(shè)備封裝:28-TSOP 包裝:帶卷 (TR) 其它名稱:71V256SA15PZGI8 |
| W25Q80BVSNIG TR | 制造商:Winbond Electronics Corp 功能描述: 制造商:Winbond Electronics Corp 功能描述:IC FLASH 8MBIT 104MHZ 8SOIC |
| W25Q80BVSNIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q80BVSSAG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q80BVSSAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。