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參數(shù)資料
| 型號： | W25Q32BVSSAG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 32M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, GREEN, SOIC-8 |
| 文件頁數(shù)： | 7/79頁 |
| 文件大小： | 1090K |
| 代理商： | W25Q32BVSSAG |
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W25Q32BV
Publication Release Date: April 01, 2011
- 15 -
Revision F
7.1.6
Complement Protect Bit (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For
instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1,
the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to
the Status Register Memory Protection table for details. The default setting is CMP=0.
7.1.7
Status Register Protect Bits (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1 SRP0
/WP
Status
Register
Description
0
X
Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and can not
be written to.
0
1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
1
0
X
Power Supply
Lock-Down
Status Register is protected and can not be written to again
until the next power-down, power-up cycle.
(1)
1
X
One Time
Program
(2)
Status Register is permanently protected and can not be
written to.
Note:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Winbond for details.
7.1.8
Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
7.1.9
Security Register Lock Bits (LB3, LB2, LB1)
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB[3:1] is 0, Security Registers are unlocked. LB[3:1] can be set to 1 individually using the
Write Status Register instruction. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
相關PDF資料 |
PDF描述 |
|---|---|
| W25Q32BVSSAP | 32M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q32BWSNIP | 4M X 8 SPI BUS SERIAL EEPROM, DSO8 |
| W25Q32BWSSIG | 4M X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q40BWSNIP | 4M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q64BVSSIP | 8M X 8 SPI BUS SERIAL EEPROM, PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q32BVSSAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q32BVSSIG | 功能描述:IC SPI FLASH 32MBIT 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| W25Q32BVSSIG TR | 制造商:Winbond Electronics Corp 功能描述:SPIFLASH, 32M-BIT, 4KB UNIFORM |
| W25Q32BVSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q32BVTCAG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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