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參數資料
| 型號： | VSP3000Y |
| 英文描述： | 12-Bit, 6MHz CCD/CIS SIGNAL PROCESSOR |
| 中文描述： | 12位，6MHz的防治荒漠化公約/ CIS信號處理器 |
| 文件頁數： | 12/13頁 |
| 文件大?。?/td> | 145K |
| 代理商： | VSP3000Y |
12
VSP3000
PROGRAMMING THE VSP3000
The VSP3000 consists of three CCD or CIS channels and a 12-
bit A/D converter. Each channel (red, green, and blue) has its
own 8-bit offset and 5-bit gain adjustable registers to be
programmed by the user. There is also a 7-bit Configuration
Register on-chip to program the different operation modes.
These registers are as follows:
For this example, V
REF
will be 1V.
Bypass V
REF
with 10
μ
F and 0.1
μ
F capacitors when internal
reference mode is used.
Example:
A 1-channel CIS mode (red channel) with external 1.2V
reference:
= > D0 = ‘1’, D1 = X, D2 = ‘1’, D4 = ‘0’ and D5 = ‘0’
For this example, V
REF
will be an input pin, applied with
1.2V. This input will set the full-scale input of the VSP3000
at 2.4V.
Offset Registers
Offset registers control the analog offset input to the channel
prior to the PGA. There is an 8-bit Offset Register on each
channel. The offset range varies from –150mV to +50mV.
The Offset Register uses a Straight Binary code. All ‘0’s
correspond to –150mV and all ‘1’s correspond to +50mV of
the offset adjustment.
PGA Gain Registers
The PGA Gain Registers control the analog gain to the
channels prior to the A/D converter. There is a 5-bit PGA
Gain Register on each channel. The gain range varies from 1
to 4.44 (0dB to +13dB). The PGA Gain Register is a Straight
Binary code. All ‘0’s correspond to analog gain of 0dB and
all ‘1’s correspond to the analog gain of 13dB.
Offset and Gain Calibration Sequence
When the VSP3000 is powered on, it will be initialized as a
3-channel CDS, 1V internal (2V full scale) reference mode
with analog gain of 1. This mode is commonly used for CCD
scanner applications. The calibration procedure is done at the
very beginning of the scan. Once calibration is done, registers
on VSP3000 will keep this information (offset and gain for
each channel) during the operation.
To calibrate the VSP3000, use the following procedure:
Step 1: Set the VSP3000 to the proper mode.
Step 2: Set analog PGA gain to 1 (code: 00H) and offset to
0mV (code: C0H).
Step 3: Scan a dark line.
Step 4: Calculate the pixel offsets according to the ADC
output.
Step 5: Readjust input Offset Registers.
Step 6: Scan a white line.
Step 7: Calculate gain. It will be the ADC full scale divided
by the ADC output when the white line is scanned.
Step 8: Set the Gain Register. If the ADC output is not close
to full scale, go back to Step 3. The calibration is
complete if the output is close to full scale.
These Registers can be accessed by either the parallel or serial
port. In the parallel mode, the address and data port are
combined with the ADC data output pins. The data bus is
assigned as D0 to D7 (pin 25 to pin 32) and the address bus
is A0 to A2 (pin 33 to pin 35). In the serial mode, serial data
(SD), serial clock (SCLK), and write signal (WRT pin for
both parallel and serial writing) are assigned. The following
table shows how to access these modes.
Configuration Register
The Configuration Register is designed as follows:
ADDRESS
A2
A1
A0
REGISTER
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Configuration Register (7-Bit)
Red Channel Offset Register (8-Bit)
Green Channel Offset Register (8-Bit)
Blue Channel Offset Register (8-Bit)
Red Channel Gain Register (5-Bit)
Green Channel Gain Register (5-Bit)
Blue Channel Gain Reigster (5-Bit)
Reserved
OE
P/S
MODE
0
0
1
1
0
1
0
1
A/D Data Output Enabled, Serial Mode Enabled
Prohibit Mode
A/D Data Output Disabled, Serial Mode Enabled
A/D Data Output Disabled, Parallel Mode Enabled
BIT
LOGIC ‘0’
LOGIC ‘1’
D0
D1
D2
D3
CDS Mode
V
REF
= 1V
Internal Reference
3-Channel, D4 and D5 Disabled
CIS Mode
V
REF
= 1.5V
External Reference
1-Channel, D4 and D5 Enabled
D4
D5
0
0
Red Channel
0
1
Green Channel
1
0
Blue Channel
1
1
XXXXXXXX
D6
D7
R > G > B MUX Sequence
XXXXXXXX
B > G > R MUX Sequence
XXXXXXXX
For Reading/Writing to the Configuration Register, the ad-
dress will be:
A2 = ‘0’, A1 = ‘0’, and A0 = ‘0’
Example:
A 3-channel CDS with internal reference V
REF
= 1V (2V full-
scale input), the mode will be:
= > D0 = ‘0’, D1 = ‘0’and D3 = ‘0’
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相關代理商/技術參數 |
參數描述 |
|---|---|
| VSP3010 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit, 12MHz CCD/CIS SIGNAL PROCESSOR |
| VSP3010Y | 功能描述:視頻模擬/數字化轉換器集成電路 12-Bit 12Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP3010Y/2K | 功能描述:視頻模擬/數字化轉換器集成電路 12-Bit 12Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP3010Y/2KG4 | 功能描述:視頻模擬/數字化轉換器集成電路 12-Bit 12Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP3010YG4 | 功能描述:視頻模擬/數字化轉換器集成電路 12-Bit 12Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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