參數(shù)資料
型號(hào)： VSP2582RHNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC36
封裝： GREEN, PLASTIC, QFN-36
文件頁(yè)數(shù)： 9/22頁(yè)
文件大?。?/td> 435K
代理商： VSP2582RHNR
POWER SUPPLY, GROUNDING AND DEVICE DECOUPLING RECOMMENDATIONS
www.ti.com................................................................................................................................................. SBES002A – JUNE 2008 – REVISED SEPTEMBER 2008
A-PGA Register (Address: h008)
CDS Gain control
D2
D1
D0
ANALOG GAIN
0
0 dB (default)
0
1
3 dB
0
1
0
6 dB
0
1
9 dB
1
–3 dB
NOTE:
Other values of D[2:0] are not applicable.
Power Register (Address: h009)
DATA BIT
NAME
DESCRIPTION
DEFAULT
D[1:0]
OB loop IDAC output current
00: x1, 01: x2, 10: x4, 11: x8
00
D[2]
CDS Power Trim
0: Normal CDS Power, 1: Reduce CDS Power
0
D[3]
ADC Power Trim
0: Normal ADC Power, 1: Reduce ADC Power
0
D[4]
Ref Power Trim
0: Normal Ref Power, 1: Reduce Ref Power
0
The VSP2582 incorporates a high-precision, high-speed analog-to-digital converter and analog circuitry that is
vulnerable to any extraneous noise from the rails or elsewhere. For this reason, although the VSP2582 has
multiple supply pins, it should be treated as an analog component; all supply pins except for VDD should be
powered by only the analog supply of the system. This configuration ensures the most consistent results,
because digital power lines often carry high levels of wideband noise that would otherwise be coupled into the
device and degrade achievable performance.
Proper grounding, short lead length, and proper use of ground planes are also very important for high-frequency
designs. Multilayer printed circuit boards (PCBs) are recommended for best performance because they offer
distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers, etc. It is
highly recommended that the analog and digital ground pins of the VSP2582 be joined together at the IC and be
connected only to the analog ground of the system. The driver stage of the digital outputs (B(9:0]) is supplied
through a dedicated supply pin (VDD) and should be separated from the other supply pins completely, or at least
with a ferrite bead. It is also recommended to keep the capacitive loading on the output data lines as low as
possible (typically less than 15 pF). Larger capacitive loads demand higher charging current as a result of surges
that can feed back into the analog portion of the VSP2582 and affect performance. If possible, external buffers or
latches should be used that provide the added benefit of isolating the VSP2582 from any digital noise activities
on the data lines. In addition, resistors in series with each data line may help minimize surge current.
Because of the high operating speed, the converter also generates high-frequency current transients and noises
that are fed back into the supply and reference lines. This interference requires the supply and reference pins to
be sufficiently bypassed. In most cases, a 0.1-
F ceramic-chip capacitor is adequate to decouple the reference
pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum (1
F to 22
F) and ceramic (0.1 F) capacitors. The effectiveness of the decoupling largely depends on the proximity to the
individual pin. VDD should be decoupled to the proximity of DGND. Special attention must be paid to the
bypassing of COB and BYPP because these capacitor values determine the important analog performance of the
device. Although the recommend capacitor values for COB and BYPP are 0.1
F and 1000 pF, respectively, it is
better to adjust the capacitor for BYPP at the case.
Copyright 2008, Texas Instruments Incorporated
17
Product Folder Link(s): VSP2582
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