參數(shù)資料
型號(hào)： VSP2582RHNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC36
封裝： GREEN, PLASTIC, QFN-36
文件頁(yè)數(shù)： 8/22頁(yè)
文件大小： 435K
代理商： VSP2582RHNR
SBES002A – JUNE 2008 – REVISED SEPTEMBER 2008................................................................................................................................................. www.ti.com
Clk-Pol-ctrl Register (Address: h000)
Clk-Pol-ctrl selects the active polarity of CLPDM, CLPOB, and SHP/SHD.
DATA BIT
NAME
DESCRIPTION
DEFAULT
D3
CLPDM Polarity
0 : Active Low
1 : Active High
0
D4
CLPOB Polarity
0 : Active Low
1 : Active High
0
D5
SHP/SHD Polarity
0 : Active Low
1 : Active High
0
AFE-ctrl(1) Register (Address: h001)
DATA BIT
NAME
DESCRIPTION
DEFAULT
D0
Standby
0: Normal operation
1: standby
0
D3
Test enable
0: disable
1: enable
0
AFE-ctrl(2) Register (Address: h002)
AFE-ctrl(2) register controls the following data output settings.
DATA BIT
NAME
DESCRIPTION
DEFAULT
D[1:0]
Data output delay
00: 0 ns, 01: 2 ns, 10: 4 ns, 11: 6 ns
0
D4
Output enable
0: enable
1: Hi-Z
0
S-delay Register (Address: h003)
S-delay register controls SHD sampling start time from the rising edge or SHP.
DATA BIT
NAME
DESCRIPTION
DEFAULT
D[1:0]
Sampling delay for SHD
00: 0 ns, 01: 2 ns (10, 11 are not allowed)
0
Clamp Register (Address: h004)
D4
D3
D2
D1
D0
CLAMP LEVEL (VSP2582)
0
64 LSB
0
1
72 LSB
:
0
1
120 LSB
0
1
0
128 LSB (default)
0
1
0
1
136 LSB
:
1
0
304 LSB
1
312 LSB
Hot-pixel Register (Address: h005)
DATA BIT
NAME
DESCRIPTION
DEFAULT
Hot pixel rejection level is givens following
equation.
D[4:0]
Hot pixel rejection level
11111
RL (LSB) = 16 (d[4:0] + 1)
Where: RL is level difference from OB level.
D5
Hot pixel rejection disable
0: disable
1: enable
1
D-PGA Register (Address: h006 and h007)
D-PGA_U
D-PGA_L
ANALOG GAIN
DEFAULT
Digital PGA gain is givens following equation.
Gain (dB) = (D-PGA 0.03125 ) – 6
D[3:0]
D[5:0]
Where: D-PGA is decimal value of 10-bit data
D-PGA = 00 1100 000 = 0 dB
which is combined D-PGA_U and D-PGA_L.
D-PGA_U is MSB side of D-PGA.
16
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): VSP2582
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