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參數(shù)資料
| 型號： | VSP2582RHNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC36 |
| 封裝： | GREEN, PLASTIC, QFN-36 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 435K |
| 代理商： | VSP2582RHNR |
TIMING SPECIFICATIONS
t
WP
CCD
N
N+1
N+2
N+3
t
PD
t
WD
t
WD
t
S
t
S
t
CKP
t
ADC
t
ADC
t
INHIBIT1
t
INHIBIT2
t
OD
SHP
SHD
ADCCK
B0-B9
N
6
-
N
5
-
N
4
-
N
3
-
TIMING CHARACTERISTICS (36-MHz Operation)
TIMING CHARACTERISTICS (27-MHz Operation)
www.ti.com................................................................................................................................................. SBES002A – JUNE 2008 – REVISED SEPTEMBER 2008
Figure 1. TG High-Speed Pulse Specifications
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tCKP
Clock period
27.7
ns
tADC
ADCCK high or low level
6.5
13.8
21.2
ns
tWP
SHP pulse width
5.9
6.9
ns
tWD
SHD pulse width
5.9
6.9
ns
tPD
SHP trailing edge to SHD leading edge
5.0
6.9
ns
tDP
SHD trailing edge to SHP leading edge
5.2
6.9
ns
tS
Sampling delay
3
ns
Inhibited clock period 1 (from rising edge of SHP to rising
tINHIBIT1
–9
13
ns
edge of ADCCK)
Inhibited clock period 2 (from rising edge of SHD to rising
tINHIBIT2
–8
–0
ns
edge of ADCCK)
tOD
Output delay
0
5
ns
DL
Data latency
6
Clocks
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tCKP
Clock period
37
ns
tADC
ADCCK high or low level
6.5
18.5
30.5
ns
tWP
SHP pulse width
5.9
6.9
ns
tWD
SHD pulse width
5.9
6.9
ns
tPD
SHP trailing edge to SHD leading edge
5.9
6.9
ns
tDP
SHD trailing edge to SHP leading edge
5.2
6.9
ns
tS
Sampling delay
3
ns
Inhibited clock period 1 (from rising edge of SHP to rising
tINHIBIT1
–9
13
ns
edge of ADCCK)
Inhibited clock period 2 (from rising edge of SHD to rising
tINHIBIT2
–8
–0
ns
edge of ADCCK)
tOD
Output delay
0
5
ns
DL
Data latency
6
Clocks
Copyright 2008, Texas Instruments Incorporated
7
Product Folder Link(s): VSP2582
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