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參數(shù)資料
| 型號： | VSP2582RHNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC36 |
| 封裝： | GREEN, PLASTIC, QFN-36 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 435K |
| 代理商： | VSP2582RHNR |
T=C/(16384
I
)
MIN
(1)
SR=I
/C
MAX
(2)
SBES002A – JUNE 2008 – REVISED SEPTEMBER 2008................................................................................................................................................. www.ti.com
At the CDS circuit, the CCD offset is compensated as a difference between the reference level and the data level
of the OB pixel. The compensated signal levels are recognized as actual OB levels, and outputs are clamped to
OB levels set by the serial interface. These OB levels are the base of black for the effective pixel period
thereafter.
Since the DPGA is a gain stage outside the OB loop, OB levels are not affected even when the gain changes.
The converging time of the OB loop is determined based on the capacitor value connected to the COB terminal
and the output from the current output data-to-analog converter (DAC) of the loop. The time constant can be
obtained from following equation:
xxx
Where C is the capacitor value connected to COB, and IMIN is minimum current (0.15 A) of the current DAC.
which is a current equivalent to 1 LSB of the DAC output. When C = 0.1
F, T will be 40.7 s. The slew rate, SR,
can be obtained from following equation:
xxx
Where, C is the capacitor value connected to COB, and IMAX is maximum current (153 A) of the current DAC,
with a current equivalent to 1023 LSB of the DAC output.
DAC output current multiplication is provided. This function increases the DAC output current through the serial
interface at x2, x4 and x8. Increased DAC current shortens the time constant of the OB loop. This function is
effective when a particular OB level changes significantly and requires fast loop setting.
On device power up, the COB capacitor voltages have not charged. For fast start up, a COB voltage boost-up
circuit is provided.
The OB clamp level (digital output value) can be set from an external source through the serial interface by
inputting a digital code to the OB clamp level register. The digital code to be input and the corresponding OB
clamp level are shown in Table 2.
Table 2. Input Code and OB Clamp Level to be Set
CLAMP LEVEL
CODE
VSP2582 (12-BIT)
0 0000 (default)
64 LSB
0 0001
72 LSB
:
0 0110
112 LSB
0 0111
120 LSB
0 1000 (default)
128 LSB
0 1001
136 LSB
:
1 1110
304 LSB
1 1111
312 LSB
12
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): VSP2582
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