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參數(shù)資料
| 型號： | VSP2000 |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 291K |
| 代理商： | VSP2000 |
VSP2000
7
THEORY OF OPERATION
The VSP2000 is an integrated circuit that contains many of
the key features associated with the processing of analog
signals in a video camera or digital still camera. Figure 1
shows a simplified block diagram of the VSP2000.
The output from the CCD array is first sent to a correlated
double sampler (CDS), a voltage-controlled attenuator with
a logarithmic control characteristic, and an output amplifier
prior to being applied to the input of a 10-bit analog-to-
digital converter.
Two calibration cycles are employed to reduce the offset
variation of the VSP2000. During the dummy pixel time, an
input auto-zero circuit is activated that eliminates the offset
of the correlated double sampler. During the optical black
timing interval, another auto-zero circuit is employed to
eliminate the offset associated with the output amplifier and
the remaining offset from the CDS.
CORRELATED DOUBLE SAMPLER (CDS)
The CDS removes low frequency noise from the output of
the image sensor. Refer to Figure 2 which shows a block
diagram of the CDS. The output from the CCD array is
sampled during the reference interval as well as during the
data interval. Noise that is present at the input and is of a
period greater than the pixel interval will be eliminated by
subtraction.
The VSP2000 employs a three track/hold correlated double
sampler architecture. Track/Hold 2 is sampled during the
reference interval by the REFCK signal. Track/Hold 3 is
resampled at the same time that the data Track/Hold 1 is
sampled by the DATCK signal. This is done to remove large
transients from Track/Hold 2 that results from a portion of
the reset transient being present during the acquisition time
of this track and hold. The output of Track/Hold 2 is buffered
by a voltage follower.
FIGURE 2. Block Diagram of Correlated Double Sampler.
FIGURE 1. Simplified Block Diagram of VSP2000.
Data Sampling Channel
Reference Sampling
Channel
T/H1
T/H3
T/H2
1V
DUMC REFCK
CCD
Input
DATCK
To VCA
10-Bit
18MHz
A/D
VCA
CDS
Clamp
REFCK DATCK
Black Level
Auto-Zero
Loop
Dummy
Feedback
Loop
OB
Gain Control
DUMC
CCD Input
Output
Amplifier
Digital Output
ADCK
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| VSP2080 | CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
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| VSP2101 | CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2101Y | CCD SIGNAL PROCESSOR For Digital Cameras |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2000Y | 制造商:Rochester Electronics LLC 功能描述:CCD SIGNAL PROCESSOR - Bulk |
| VSP2050 | 功能描述:臺式電源 20V 50A HIGH POWER SWITCHING WITH RS232 RoHS:否 制造商:B&K Precision 類型:DC Electronic Loads (Programmable) 輸入電壓:110 VAC, 220 VAC Selectable 輸出端數(shù)量: 輸出電壓（通道 1）:0.1 V to 120 V 輸出電流（通道 1）:30 A 輸出電壓（通道 2）: 輸出電流（通道 2）: 輸出電壓（通道 3）: 輸出電流（通道 3）: 顯示器類型:VFD |
| VSP2050GPIB | 功能描述:臺式電源 20V 50A HIGH POWER SWITCHING WITH GPIB RoHS:否 制造商:B&K Precision 類型:DC Electronic Loads (Programmable) 輸入電壓:110 VAC, 220 VAC Selectable 輸出端數(shù)量: 輸出電壓（通道 1）:0.1 V to 120 V 輸出電流（通道 1）:30 A 輸出電壓（通道 2）: 輸出電流（通道 2）: 輸出電壓（通道 3）: 輸出電流（通道 3）: 顯示器類型:VFD |
| VSP2050-REFURB | 制造商:B&K Precision Corporation 功能描述:POWER SUPPLY, BENCH, 20V, 1.2KW; Power Supply Output Type:Adjustable; No. of Outputs:1; Power Rating:1.2kW; Input Voltage:95VAC to 264VAC; Height:44.5mm; Length:457mm; Load Regulation:0.1%; Output Current:50A; Output Voltage:20VDC ;RoHS Compliant: NA |
| VSP2080 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
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