
VSP2000
3
+V
....................................................................................................... +6V
Analog Input.........................................................(0 –0.3V) to (+V
S
+0.3V)
Logic Input ...........................................................(0 –0.3V) to (+V
+0.3V)
Case Temperature ......................................................................... +100
°
C
Junction Temperature .................................................................... +150
°
C
Storage Temperature ..................................................................... +150
°
C
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE DRAWING
NUMBER
(1)
TEMPERATURE
RANGE
PRODUCT
PACKAGE
VSP2000
48-Lead LQFP
340
–40
°
C to +85
°
C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
27
28
29
30
31
32
33
34
CCD R
AV
AGC1
AGC2
AV
SS3
LCM
AV
DD1
INT BIAS 2
Capacitor for Dummy Feedback Loop
Analog Ground
Sets Gain of CCD Channel, 1k
Resistor
Sets Gain of CCD Channel, 16k
Resistor
Analog Ground
Attenuator Common-Mode Bypass
Analog +Supply
Internal Bias, should be connected to GND
with 0.1
μ
F Capacitor
Analog Ground
Internal Bias, should be connected to GND
with 0.1
μ
F Capacitor
Attenuator Ladder Bypass
ADS Common-Mode Voltage
Analog +Supply
Analog +Supply
Digital Ground
Analog +Supply
Analog +Supply
Analog +Supply
Analog Ground
Analog Ground
ADS –Reference, Bypass to Ground
ADS +Reference, Bypass to Ground
35
36
AV
INT BIAS 1
37
38
39
40
41
42
43
44
45
46
47
48
2.4V
CM
AV
DD2
AV
DD3
DV
SS
AV
DD
AV
DD4
AV
DD5
AV
SS4
AV
REFN
REFP
1
2
3
4
5
6
7
8
9
DV
SS1
B10 (LSB)
B9
B8
B7
B6
B5
B4
B3
B2
B1 (MSB)
DRV
DD
DRV
SS
DV
SS2
DV
ADCK
DV
DD1
PD
PB
OB
REFCK
DATCK
DUMC
C
AV
SS1
CCD D
Digital Ground
LSB of ADS
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
MSB of ADS
Digital +Supply of ADS Output
Digital Ground for ADS Output
Digital Ground
Digital Ground
ADS Clock, Data Output on Falling Edge
Digital +Supply
L = Normal Operation, H = Reduced Power
L = –FS + 32 LSB, H = Normal at CCD Mode
Optical Black Clamp Pulse, Active LOW
Neg Pulse, Trailing Edge Samples Reset
Neg Pulse, Trailing Edge Samples Data
Dummy Clamp, Active LOW
Capacitor for Optical Feedback
Analog Ground
CCD Signal Input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIN CONFIGURATION
PIN
DESIGNATOR
DESCRIPTION
PIN
DESIGNATOR
DESCRIPTION
PIN DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
INT BIAS1
AV
SS
INT BIAS2
AV
DD1
LCM
AV
SS3
AGC2
AGC1
AV
SS2
CCD R
CCD D
AV
SS1
R
R
A
S
A
S
A
D
A
D
A
D
D
S
A
D
A
D
C
2
D
S
D
S
D
S
A
D
D
1
P
P
O
R
D
D
C
1
2
3
4
5
6
7
8
9
10
11
12
DV
SS1
B10 (LSB)
B9
B8
B7
B6
B5
B4
B3
B2
B1 (MSB)
DRV
DD
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
VSP2000