參數(shù)資料
型號: VND5E012AYTR-E
廠商: STMICROELECTRONICS
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO36
封裝: ROHS COMPLIANT, SSOP-36
文件頁數(shù): 17/37頁
文件大?。?/td> 924K
代理商: VND5E012AYTR-E
Application information
VND5E012AY-E
Doc ID 13621 Rev 2
3
Application information
Figure 32. Application schematic
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCCPK max rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO T/R 7637/1 table.
3.2
MCU I/Os protection
When negative transients are present on the VCC line, the control pins is pulled negative to
approximatly -1.5 V. ST suggests to insert a resistor (Rprot) in line to prevent the
microcontroller I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
-VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH ) / IIHmax
Calculation example:
For VCCpeak = - 1.5 V; Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V
VCC
GND
OUTPUT
Dld
μC
+5V
CS_DIS
IINPUT
Rprot
CURRENT SENSE
Rprot
RSENSE
Cext
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