參數(shù)資料
型號(hào)： VMS115
元件分類： 加密電路
英文描述： TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100
封裝： MQFP-100
文件頁數(shù)： 64/64頁
文件大?。?/td> 572K
代理商： VMS115
VLSI Technology, a subsidiary of Philips Semiconductors
8/10/99
9
Revision: 2.3
906
Data Sheet
5.1.2.1
Block Architecture
The design is an optimized DES engine that can be utilized for both single and triple DES opera-
tions. The single DES operates per the FIPS-PUB standard. The triple DES function operates as
either a two-key or three-key operation. The triple DES encryption cycle includes three ciphering
sessions which start with the encryption of the plain text using Key 0. The result is, then,
decrypted with Key 1 before encrypted again with Key 2. For two-key triple DES operations,
Key 0 will be the same as the Key 2. The triple DES decryption cycle is the opposite of the
encryption cycle.
Cipher_Text = Encrypt_Key2[Decrypt_Key1[Encrypt_Key0[Plain_Text]]]
Plain_Text = Decrypt_Key0[Encrypt_Key1[Decrypt_Key2[Cipher_Text]]]
The block uses a 64 bit Initialization Vector (IV) register for the CBC mode.
5.1.2.2
Triple DES Throughput
The DES Core requires 24 clock cycles for Triple DES processing through the DES engine. The
internal state machine takes one clock cycle to latch a 64 bit block of data into the engine and
another cycle to latch a 64 bit of data out of the engine.
Triple DES Pipeline Diagram
Triple DES Processing Cycles
Function
Description
Clock Cycles
Load Context
21
A
Load In-Place Buffer.
3
B
Load Word Align Buffer.
3
CLoad DES Core.
1
D
Triple DES Processing.
24
E
Unload DES Core.
1
F
Load Data Into In-Place Buffer.
8
A
B
D
F
CE
51
84
59
Clock Cycles
A
B
D
F
CE
Load Context
21
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