參數(shù)資料
型號(hào)： VMS115
元件分類： 加密電路
英文描述： TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100
封裝： MQFP-100
文件頁(yè)數(shù)： 18/64頁(yè)
文件大?。?/td> 572K
代理商： VMS115
VLSI Technology, a subsidiary of Philips Semiconductors
8/10/99
25
Revision: 2.3
906
Data Sheet
5.3.1.3
Configuration Register
Bits 31-16 Reserved
Bits 15:8
Chip ID - This byte identifies the version of the chip.
Bits 7-1
Reserved
Bit 0
Soft Reset - Reset the VMS115 chip. Equivalent to the Reset input pin. When the
reset is complete, this bit is set to 0.
5.3.2
Reset
Reset can be initiated via the input Reset pin going high or the Reset bit in the Configuration Reg-
ister above. When resetting via the input Reset pin, the input must be held high for a minimum of
one clock cycle to ensure that the VMS115 will exit Reset properly.
The RESET input signal can be asserted and de-asserted asynchronously to the clock input signal.
The VMS115 will re-synchronize the RESET input and hold the part in reset for at least 3 clocks.
Thus, the VMS115 will be ready to respond to external commands (register, context, or packet)
within 4 clocks of RESET being de-asserted or 6 clocks after a write to the soft reset bit in the
Configuration register.
5.3.3
Power Management
The ZZ input (active high) is used to put the VMS115 part into a low power mode. The ZZ input
can be asserted asynchronously to the clock input signal. The ZZ input will be re-synchronized to
the clock input and then gated into the master clock line prior to the clock tree of the device.
Internal logic will guarantee that the clock is stopped on a low phase and effectively ‘stretched’
without glitching. The internal VMS115 clock will be stretched within 5 clocks of the assertion
of the ZZ input. The internal VMS115 clock will resume within 5 clocks of the de-assertion of
the ZZ input.
The VMS115 makes no assumption of the contents of the internal data after a power down cycle
unless the interface is not active throughout the power down cycle. The chip select input must be
de-asserted 5 clocks prior to the assertion of ZZ and remain inactive until 5 clocks after the de-
assertion of ZZ to ensure that the internal data states are not corrupted by the power-down cycle.
One exception to this is the Exponentiator Result RAM contents which are NOT valid following a
sleep mode cycle.
Configuration Register Configuration
15
14
13
12
11
10
9
8
Chip ID
7
6
5
4
3
2
1
0
Reserved
Soft Reset
相關(guān)PDF資料
PDF描述
VN-84-AR-1 9800 MHz - 10400 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS
VN-84-ARD-1 9800 MHz - 10400 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS
VN-84-AS-1 9800 MHz - 10400 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS
VN-86-AR-1 10000 MHz - 10500 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS
VN-86-ARD-1 10000 MHz - 10500 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VMS1177 制造商:CPI 制造商全稱:CPI 功能描述:Magnetron
VMS1197B 制造商:CPI 制造商全稱:CPI 功能描述:Magnetron
VMS128K8MB-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module
VMS128K8MC-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module
VMS128K8MF-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*