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參數(shù)資料
| 型號(hào)： | VMS115 |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 63/64頁 |
| 文件大?。?/td> | 572K |
| 代理商： | VMS115 |
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VLSI Technology, a subsidiary of Philips Semiconductors
8/10/99
8
Revision: 2.3
906
Data Sheet
5 Functional Description
This section will describe the functionality of the chip, interfaces to the functions and a register
summary for the interfaces.
5.1
IPSec Processor
This functionality includes DES, 3DES, SHA-1 hashing and MD5 hashing. Parallel processing of
data through the encryption and hash engines is supported. IPSec HMAC processing is also sup-
ported with this block.
5.1.1
Main Features
Supports Electronic Codebook (ECB) and Cipher Block Chaining (CBC) ciphering
operation.
Supports two operating modes: Single and triple DES (two key and three key types).
Based on a design validated by the National Institute of Standards and Technology
(NIST)
HMAC processing supported.
MD5 or SHA-1 hashing of clear and encrypted data.
IPSec Block Diagram
5.1.2
DES Engine
This DES core is a subset of VLSI’s standard VK110 DES core. This block is a high speed
ciphering engine that supports the Data Encryption Standard (DES) algorithm as specified by the
National Institute of Standards and Technology's (NIST) Federal Information Processing Stan-
dards Publication #46-2 (FIPS PUB 46-2). It offers two modes of ciphering, Electronic Code
Book (ECB) and Cipher Block Chaining (CBC), and two operating modes, single and triple DES.
The triple DES function supports both two-key and three-key. The aforementioned ECB mode
will be implemented in accordance with FIPS-PUB 81.
DES Engine
(DES, 3DES)
Hash Engine
(MD5, SHA-1)
16x4 Byte
In-Place
Buffer
Hash Digest
Output
Buffer
Mux
SSRAM
Interface
ORDY
IRDY
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