參數(shù)資料
型號: VG36641641DTL-8H
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS Synchronous Dynamic RAM
中文描述: 同步動態(tài)隨機(jī)存儲器的CMOS
文件頁數(shù): 13/69頁
文件大?。?/td> 1364K
代理商: VG36641641DTL-8H
Document :1G5-0177
Rev.2
Page 13
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
(3/3)
Notes
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if t
RCD
is not satisfied.
6. Illegal if t
RAS
is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy t
DPL
.
10. Illegal if t
RRD
is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
Current
CS
RAS
CAS
WE
Address
Command
Action
Write
recovering
H
X
X
X
X
DESL
Nop
Enter row active after t
DPL
Enter row active after t
DPL
L
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
Nop
Enter row active after t
DPL
L
L
L
L
L
L
H
H
H
L
L
L
L
X
L
L
H
H
L
L
X
H
L
H
L
H
L
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
READ/READA
WRIT/WRITA
ACT
PRE/PALL
PEF/SELF
MRS
DESL
Start read, Determine AP
New write, Determine AP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
8
3
3
Write
recovering
with auto
precharge
Nop
Enter precharge after t
DPL
Enter precharge after t
DPL
L
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
Nop
Enter precharge after t
DPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop Enter idle after t
RC
Nop Enter idle after t
RC
ILLEGAL
ILLEGAL
L
L
L
L
L
L
H
H
H
L
L
L
L
X
L
L
H
H
L
L
X
H
L
H
L
H
L
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
3,8,11
3,11
3,11
3
Auto
Refreshing
L
H
H
X
X
NOP/BST
L
L
L
H
L
L
L
L
H
L
L
X
H
H
H
L
L
H
L
X
H
H
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS ILLEGAL
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL/
REF/SELF/MRS
Mode regis-
ter
setting
Nop
Enter idle after 2 Clocks
Nop
ILLEGAL
ILLEGAL
ILLEGAL
Enter idle after 2 Clocks
相關(guān)PDF資料
PDF描述
VG36641641DT CMOS Synchronous Dynamic RAM
VG36641641BT CMOS Synchronous Dynamic RAM
VG509A EPROM-Based 8-bit micro-controller
VGFX200K-SERIES ASIC
VGFX20K-SERIES ASIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VG3664321412BT 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM
VG36643241BT-10 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM
VG36643241BT-7 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM
VG36643241BT-8 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM
VG366440(80/16)41DT(L)-6 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM