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參數(shù)資料
| 型號： | VG36641641DTL-8H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Synchronous Dynamic RAM |
| 中文描述： | 同步動(dòng)態(tài)隨機(jī)存儲器的CMOS |
| 文件頁數(shù)： | 12/69頁 |
| 文件大?。?/td> | 1364K |
| 代理商： | VG36641641DTL-8H |
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Document :1G5-0177
Rev.2
Page 12
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
( 2/3)
Current state
CS RAS
CA
WE
Address
Command
Action
Notes
Read with auto
precharge
H
L
L
L
L
L
L
L
L
H
X
H
H
H
H
L
L
L
L
X
X
H
H
L
L
H
H
L
L
X
X
H
L
H
L
H
L
H
L
X
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
PEF/SELF
MRS
DESL
Continue burst to end
Continue burst to end
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue burst to end
recovering with auto precharte
Precharging
Precharging
11
11
3,11
3,11
Write with auto
precharge
write
L
H
H
H
X
NOP
Continue burst to end
recovering with auto precharge
write
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
11
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3,11
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - code
MRS
ILLEGAL
Precharging
H
X
X
X
X
DESL
Nop
Enter idle after t
RP
L
H
H
H
X
NOP
Nop
Enter idle after t
RP
L
H
H
L
X
BST
Nop
Enter idle after t
RP
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Nop
Enter idle after t
RP
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
Row activating
H
X
X
X
X
DESL
Nop
Enter row active after t
RCD
Enter row active after t
RCD
Enter row active after t
RCD
ILLEGAL
L
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3, 9
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
→
→
→
→
→
→
→
→
→
→
→
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