參數(shù)資料
型號: VG26VS17405J-5
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4M X 4 EDO DRAM, 50 ns, PDSO24
封裝: 0.300 INCH, PLASTIC, SOJ-26/24
文件頁數(shù): 24/27頁
文件大?。?/td> 244K
代理商: VG26VS17405J-5
Document:1G5-0162
Rev.1
Page 6
VIS
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics; 5- Volt Verion
(Ta = 0 to + 70 °C, VCC= + 5V
,VSS = 0V)
Parameter
Symbol
Test Conditions
VG26(V)(S)17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Operating current
ICC1
RAS cycling
CAS, cycling
tRC = min
-
120
-
110
mA
1, 2
Standby
Current
Low
power
S-version
ICC2
TTL interface
RAS, CAS = VIH
Dout = High-Z
-
2
-
2
mA
CMOS interface
RAS,
-0.2V
Dout = High-Z
-
0.25
-
0.25
mA
Standard
power
version
TTL interface
RAS, CAS = VIH
Dout = High-Z
2
-
2
mA
CMOS interface
RAS,
-0.2V
Dout = High-Z
1
-
1
mA
RAS-only
refresh current
ICC3
RAS cycling, CAS = VIH
tRC = min
-
120
-
110
mA
1, 2
EDO page mode
current
ICC4
tRC = min
-
90
-
80
mA
1, 3
CAS-before-RAS
refresh current
ICC5
tRC = min
RAS, CAS cycling
-
120
-
110
mA
1, 2
Self-refresh current
(S - Version)
ICC8
-
350
-
350
CAS- before- RAS long
refresh current
(S-Version)
ICC9
Standby: VCC-
CAS before RAS refresh:
2048 cycles / 128ms
RAS, CAS:
VCC-
(Max)
Dout = High-Z,
-
500
-
500
10
±
CAS
Vcc
CAS
Vcc
t
RAS
100
s
A
0.2V
RAS
0V
V
IL
0.2V
0.2V
V
IH
V
IH
t
RAS
300ns
A
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