參數(shù)資料
型號： VG26VS17405J-5
廠商： VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 4M X 4 EDO DRAM, 50 ns, PDSO24
封裝： 0.300 INCH, PLASTIC, SOJ-26/24
文件頁數(shù)： 2/27頁
文件大?。?/td> 244K
代理商： VG26VS17405J-5
Document:1G5-0162
Rev.1
Page 10
VIS
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
AC Characteristics
(
Ta = 0 to + 70°C, Vcc = 5V
% or 3.3V (+10%,-5%), Vss = 0V) *1, *2, *3, *4
Test conditions
Output load: two TTL Loads and 50pF (V CC = 5.0V
%)
one TTL Load and 30pF (VCC = 3.3V (+10%,-5%))
Input timing reference levels:
VIH = 2.4V, VIL = 0.8V (VCC = 5.0V
%); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V(+10%,-5%) )
Output timing reference levels:
VOH = 2.0V, VOL = 0.8V (VCC = 5V
%, 3.3V (+10%,-5%))
10
±
10
±
10
±
10
±
Read, Write, Read- Modify- Write and Refresh Cycles
(Common Parameters)
Parameter
Symbol
VG26(V)(S) 17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Random read or write cycle time
tRC
84
-
104
-
ns
RAS precharge time
tRP
30
-
40
-
ns
CAS precharge time in normal mode
tCPN
10
-
10
-
ns
RAS pulse width
tRAS
50
10000
60
10000
ns
5
CAS pulse width
tCAS
8
10000
10
10000
ns
6
Row address setup time
tASR
0
-
0
-
ns
Row address hold time
tRAH
8
-
10
-
ns
Column address setup time
tASC
0
-
0
-
ns
7
Column address hold time
tCAH
8
-
10
-
ns
RAS to CAS delay time
tRCD
12
37
14
45
ns
8
RAS to column address delay time
tRAD
10
25
12
30
ns
9
Column address to RAS lead time
tRAL
25
-
30
-
ns
RAS hold time
tRSH
8
-
10
-
ns
CAS hold time
tCSH
38
-
40
-
ns
CAS to RAS precharge time
tCRP
5
-
5
-
ns
10
OE to Din delay time
tOED
12
-
15
-
ns
Transition time (rise and fall)
tT
1
50
1
50
ns
11
Refresh period
tREF
-
32
-
32
ms
Refresh period (S- Version)
tREF
-
128
-
128
ms
CAS to output in Low- Z
tCLZ
0
-
0
-
ns
CAS delay time from Din
tDZC
0
-
0
-
ns
OE delay time from Din
tDZO
0
-
0
-
ns
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