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參數(shù)資料
| 型號： | VE28F008 |
| 廠商： | Intel Corp. |
| 英文描述： | 8 MBIT (1 MBIT x 8) FLASH MEMORY |
| 中文描述： | 8兆比特（1兆比特× 8）閃存 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 381K |
| 代理商： | VE28F008 |
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VE28F008
erase and byte write circuitry. Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations. With the appropriate com-
mand written to the register, standard microproces-
sor read timings output array data, access the intelli-
gent identifier codes, or output byte write and block
erase status for verification.
Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the VE28F008 blocks. This code is copied to,
and executed from, system RAM during actual flash
memory update. After successful completion of byte
write and/or block erase, code/data reads from the
VE28F008 are again possible via the Read Array
command. Erase suspend/resume capability allows
system software to suspend block erase to read
data and execute code from any other block.
FFFFF
64 Kbyte Block
EFFFF
F0000
64 Kbyte Block
DFFFF
E0000
64 Kbyte Block
CFFFF
D0000
64 Kbyte Block
BFFFF
C0000
64 Kbyte Block
AFFFF
B0000
64 Kbyte Block
9FFFF
A0000
64 Kbyte Block
8FFFF
90000
64 Kbyte Block
7FFFF
80000
64 Kbyte Block
6FFFF
70000
64 Kbyte Block
5FFFF
60000
64 Kbyte Block
4FFFF
50000
64 Kbyte Block
3FFFF
40000
64 Kbyte Block
2FFFF
30000
64 Kbyte Block
1FFFF
20000
64 Kbyte Block
0FFFF
10000
64 Kbyte Block
00000
Figure 4. Memory Map
Command User Interface and Write
Automation
An on-chip state machine controls block erase and
byte write, freeing the system processor for other
tasks. After receiving the Erase Setup and Erase
Confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
via the Status Register and RY/BY output. Byte
write is similarly controlled, after destination address
and expected data are supplied. The program and
erase algorithms of past Intel Flash memories are
now regulated by the state machine, including pulse
repetition where required and internal verification
and margining of data.
Data Protection
Depending on the application, the system designer
may choose to make the V
PP
power supply switcha-
ble (available only when memory byte writes/block
erases are required) or hardwired to V
PPH
. When
V
PP
e
V
PPL
, memory contents cannot be altered.
The VE28F008 Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V
PP
. Additionally, all functions are dis-
abled whenever V
CC
is below the write lockout volt-
age V
LKO
, or when RP is at V
IL
. The VE28F008 ac-
commodates either design practice and encourages
optimization of the processor-memory interface.
The two-step byte write/block erase Command User
Interface write sequence provides additional soft-
ware write protection.
BUS OPERATION
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Read
The VE28F008 has three read modes. The memory
can be read from any of its blocks, and information
can be read from the intelligent identifier or Status
Register. V
PP
can be at either V
PPL
or V
PPH
.
The first task is to write the appropriate read mode
command to the Command User Interface (array, in-
telligent
identifier,
or
VE28F008 automatically resets to Read Array mode
upon initial device powerup or after exit from deep
powerdown. The VE28F008 has four control pins,
two of which must be logically active to obtain
Status
Register).
The
6
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