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參數(shù)資料
| 型號： | VE28F008 |
| 廠商： | Intel Corp. |
| 英文描述： | 8 MBIT (1 MBIT x 8) FLASH MEMORY |
| 中文描述： | 8兆比特（1兆比特× 8）閃存 |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 381K |
| 代理商： | VE28F008 |
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VE28F008
EXTENDED BLOCK ERASE/BYTE
WRITE CYCLING
Intel has designed extended cycling capability into
its
ETOX
flash
memory
VE28F008 is designed for 10,000 byte write/block
erase cycles on each of the sixteen 64 Kbyte blocks.
Low electric fields, advanced oxides and minimal ox-
ide area per cell subjected to the tunneling electric
field combine to greatly reduce oxide stress and the
probability of failure. A 20 Mbyte solid-state drive us-
ing an array of VE28F008s has a MTBF (Mean Time
Between Failure) of 3.33 million hours
(1)
.
technologies.
The
AUTOMATED BYTE WRITE
The VE28F008 integrates the Quick-Pulse program-
ming algorithm of prior Intel Flash devices on-chip,
using the Command User Interface, Status Register
and Write State Machine (WSM). On-chip integration
dramatically simplifies system software and provides
processor interface timings to the Command User
Interface and Status Register. WSM operation, inter-
nal verify and V
PP
high voltage presence are moni-
tored and reported via the RY/BY output and appro-
priate Status Register bits. Figure 5 shows a system
software flowchart for device byte write. The entire
sequence is performed with V
PP
at V
PPH
. Byte write
abort occurs when RP transitions to V
IL
, or V
PP
drops to V
PPL
. Although the WSM is halted, byte
data is partially written at the location where byte
write was aborted. Block erasure, or a repeat of byte
write, is required to initialize this data to a known
value.
AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally, includ-
ing all preconditioning of block data. WSM opera-
tion, erase success and V
PP
high voltage presence
are monitored and reported through RY/BY and the
Status Register. Additionally, if a command other
than Erase Confirm is written to the device following
Erase Setup, both the Erase Status and Byte Write
Status bits will be set to ‘‘1’’s. When issuing the
Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 6 shows a
system software flowchart for block erase.
Erase typically takes 1.6 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed. A system software flowchart is
shown in Figure 7.
The entire sequence is performed with V
PP
at V
PPH
.
Abort occurs when RP transitions to V
IL
or V
PP
falls
to V
PPL
, while erase is in progress. Block data is
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
DESIGN CONSIDERATIONS
Three-Line Output Control
The VE28F008 will often be used in large memory
arrays. Intel provides three control inputs to accom-
modate multiple memory connections. Three-line
control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these control inputs, an address
decoder should enable CE, while OE should be con-
nected to all memory devices and the system’s
READ control line. This assures that only selected
memory devices have active outputs while deselect-
ed memory devices are in Standby Mode. Finally,
RP should either be tied to the system RESET, or
connected to V
CC
if unused.
RY/BY and Byte Write/Block Erase
Polling
RY/BY is a full CMOS output that provides a hard-
ware method of detecting byte write and block erase
completion. It transitions low time t
WHRL
after a
write or erase command sequence is written to the
VE28F008, and returns to V
OH
when the WSM has
finished executing the internal algorithm.
RY/BY can be connected to the interrupt input of
the system CPU or controller. It is active at all times,
not tri-stated if the VE28F008 CE or OE inputs are
brought to V
IH
. RY/BY is also V
OH
when the device
is in Erase Suspend or deep powerdown modes.
(1)
Assumptions: 10 Kbyte file written every 10 minutes. (20 Mbyte array)/(10 Kbyte file)
e
2,000 file writes before erase required.
(2000 files writes/erase)
c
(10,000 cycles per VE28F008 block)
e
20 million file writes.
(20
c
10
6
file writes)
c
(10 min/write)
c
(1 hr/60 min)
e
3.33
c
10
6
MTBF
.
11
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