參數(shù)資料
型號: V58C2256404SAE5
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 64M X 4 DDR DRAM, 0.65 ns, PDSO66
封裝: 0.400 X 0.875 INCH, ROHS COMPLIANT, PLASTIC, MS-024FC, TSOP2-66
文件頁數(shù): 15/61頁
文件大?。?/td> 920K
代理商: V58C2256404SAE5
22
V58C2256(804/404/164)SA Rev. 1.8 March 2007
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SA
Precharge Timing During Write Operation
Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require-
ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a
timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation
and a Precharge command to the same bank.
The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe
in the last valid write data. “Write recovery” is complete on the next 2nd rising clock edge that is used to strobe
in the Precharge command.
Write with Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
NOP
Write
NOP
PreA
NOP
CK, CK
Command
DQS
DQ
tRAS(min)
tRP(min)
BA
NOP
T9
T10
tWR
D0
D1
D2
D3
DQS
DQ
tWR
BA
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