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參數(shù)資料
| 型號： | V58C2256164SBLJ5B |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.65 ns, PBGA60 |
| 封裝： | LEAD FREE, MO-233, FBGA-60 |
| 文件頁數(shù)： | 7/62頁 |
| 文件大小： | 983K |
| 代理商： | V58C2256164SBLJ5B |
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ProMOS TECHNOLOGIES
V58C2256(804/404/164)SB
V58C2256(804/404/164)SB Rev. 1.0 November 2003
Auto Precharge Operation
The Auto Precharge operation can be issued by having column address A
10 high when a Read or Write
command is issued. If A
10 is low when a Read or Write command is issued, then normal Read or Write burst
operation is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once t
RAS(min) is satisfied.
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
Begin Autoprecharge
BA
ACT
R/w AP
NOP
CK, CK
Command
DQS
DQ
tRAS(min)
tRP(min)
Earliest Bank A reactivate
T9
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