參數(shù)資料
型號(hào)： V58C2256164SBLJ5B
廠商： PROMOS TECHNOLOGIES INC
元件分類(lèi)： DRAM
英文描述： 16M X 16 DDR DRAM, 0.65 ns, PBGA60
封裝： LEAD FREE, MO-233, FBGA-60
文件頁(yè)數(shù)： 35/62頁(yè)
文件大?。?/td> 983K
代理商： V58C2256164SBLJ5B
40
V58C2256(804/404/164)SB Rev. 1.0 November 2003
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SB
3. Outputs measured with equivalent load:
NOTES: (continued)
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications
are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate
for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will
effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long
as the signal does not ring back above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmit-ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value.
Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise.
7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected
to be set equal to VREF and must track variations in the DC level of VREF.
8. VID is the magnitude of the difference between the input level on CK and the input level on CK.
9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the
DC level of the same.
10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle
time at CL = 2 for -6, -7 with the outputs open.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate.
13. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, T A = 25°C,
VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they
are matched in loading.
14. Command/Address input slew rate = 0.5V/ns. For -5, -6, and -7 with slew rates 1V/ns and faster, tIS and tIH are
reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS and tIH has an additional 50ps per
each 100mV/ns reduction in slew rate from the 500mV/ns. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
15. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input
reference level for signals other than CK/CK is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE 0.3 x VDDQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins
driving (LZ).
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
Output
(VOUT)
VTT
50
Reference
Point
30pF
相關(guān)PDF資料
PDF描述
V58C2256404SCLS7I 64M X 4 DDR DRAM, 0.75 ns, PBGA60
V58C2256404SHUT6E 64M X 4 DDR DRAM, PDSO66
V58C2256804SHLJ5E 32M X 8 DDR DRAM, PBGA60
V58C2256804SHUE6E 32M X 8 DDR DRAM, PDSO66
V58C2256804SHUR6 32M X 8 DDR DRAM, PBGA60
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V58C2256324SAB30 制造商:Marvell 功能描述:Marvell V58C2256324SAB30
V58C2256324SAB33 制造商:Marvell 功能描述:Marvell V58C2256324SAB33
V58C2256324SAB36 制造商:Marvell 功能描述:Marvell V58C2256324SAB36
V58C2256324SAH30 制造商:Marvell 功能描述:Marvell V58C2256324SAH30
V58C2256324SAH33 制造商:Marvell 功能描述:Marvell V58C2256324SAH33
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*