參數(shù)資料
型號: V54C365164VCT8PC
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 52/54頁
文件大?。?/td> 1570K
代理商: V54C365164VCT8PC
7
V54C365164VC Rev. 0.8 July 2001
MOSEL VITELIC
V54C365164VC
Address Input for Mode Set (Mode Register Operation)
A11
A3
A4
A2
A1
A0
A10 A9
A8
A7
A6
A5
Address Bus (Ax)
BT
Burst Length
CAS Latency
Mode Register
CAS Latency
A6
A5
A4
Latency
0
Reserve
0
1
Reserve
010
2
011
3
100
4
1
0
1
Reserve
1
0
Reserve
1
Reserve
Burst Length
A2
A1
A0
Length
Sequential
Interleave
000
1
001
2
010
4
011
8
1
0
Reserve
1
0
1
Reserve
1
0
Reserve
1
Full Page
Reserve
Burst Type
A3
Type
0
Sequential
1
Interleave
Operation Mode
BA1 BA0 A11 A10 A9 A8 A7
Mode
0000
0
Burst Read/Burst
Write
0000
1
0
Burst Read/Single
Write
Operation Mode
BA0
BA1
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle latch-
es the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random col-
umn accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more
banks are activated
sequentially,
interleaved
bank
read
or
write
operations are possible. With the programmed burst
length, alternate access and precharge operations
on two or more banks can realize fast serial data
access modes among many different pages. Once
two or more banks are activated, column to column
interleave operation can be done between different
pages.
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