參數(shù)資料
型號(hào): V54C365164VCT8PC
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 1/54頁
文件大?。?/td> 1570K
代理商: V54C365164VCT8PC
MOSEL VITELIC
1
V54C365164VC
HIGH PERFORMANCE 166/143/125 MHz
3.3 VOLT 4M X 16 SYNCHRONOUS DRAM
4 BANKS X 1Mbit X 16
V54C365164VC Rev. 0.8 July 2001
PRELIMINARY
6
7
8PC
System Frequency (fCK)
166 MHz
143 MHz
125 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
8 ns
Clock Access Time (tAC3) CAS Latency = 3
5.4 ns
6 ns
Clock Access Time (tAC2) CAS Latency = 2
5.5 ns
6 ns
Clock Access Time (tAC1) CAS Latency = 1
13 ns
Features
I 4 banks x 1Mbit x 16 organization
I High speed data transfer rates up to 166 MHz
I Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
I Single Pulsed RAS Interface
I Data Mask for byte Control
I Four Banks controlled by BA0 & BA1
I Programmable CAS Latency: 1, 2, & 3
I Programmable Wrap Sequence: Sequential or
Interleave
I Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
I Multiple Burst Read with Single Write Operation
I Automatic and Controlled Precharge Command
I Random Column Address every CLK (1-N Rule)
I Suspend Mode and Power Down Mode
I Auto Refresh and Self Refresh
I Refresh Interval: 4096 cycles/64 ms
I Available in 54 Pin 400 mil TSOP-II
I LVTTL Interface
I Single +3.3 V ±0.3 V Power Supply
Description
The V54C365164VC is a four bank Synchronous
DRAM organized as 4 banks x 1Mbit x 16. The
V54C365164VC achieves high speed data transfer
rates up to 166 MHz by employing a chip architec-
ture that prefetches multiple bits and then synchro-
nizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
6
7
8PC
Std.
L
0
°C to 70°C
Blank
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