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參數(shù)資料
| 型號： | V54C3128 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128Mbit SDRAM 3.3 VOLT, BGA PACKAGE |
| 中文描述： | 128Mbit SDRAM的3.3伏，BGA封裝 |
| 文件頁數(shù)： | 14/45頁 |
| 文件大?。?/td> | 871K |
| 代理商： | V54C3128 |
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14
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Notes for AC Parameters:
1.
For proper power-up see the operation section of this data sheet.
2.
AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between V
IH
and V
IL
. All ACmeasurements assume t
T
= 1ns with the AC output load circuit shown
in Figure 1.
4.
If clock rising time is longer than 1 ns, a time (t
T
/2
–
0.5) ns has to be added to this parameter.
5.
If t
T
is longer than 1 ns, a time (t
T
–
1) ns has to be added to this parameter.
6.
These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
7.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
Read Cycle
21
t
OH
Data Out Hold Time
3
–
3
–
3
–
3
–
ns
2
22
t
LZ
Data Out to Low Impedance Time
1
–
1
–
1
–
0
–
ns
23
t
HZ
Data Out to High Impedance Time
3
6
3
7
3
7
3
8
ns
7
24
t
DQZ
DQM Data Out Disable Latency
–
2
–
2
–
2
–
2
CLK
Write Cycle
25
t
WR
Write Recovery Time
2
–
2
–
2
–
2
–
CLK
26
t
DQW
DQM Write Mask Latency
0
–
0
–
0
–
0
–
CLK
#
Symbol
Parameter
Limit Values
Unit
Note
-6
-7PC
-7
-8PC
Min. Max. Min. Max. Min. Max. Min. Max.
1.4V
1.4V
tCS
tCH
tAC
tAC
tLZ
tOH
tHZ
CLK
COMMAND
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
VIH
VIL
t
T
Figure 1.
tCK
AC Characteristics
(Cont
’
d)
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