參數(shù)資料
型號(hào): V54C3128164VB6
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝: WBGA-60
文件頁(yè)數(shù): 36/45頁(yè)
文件大?。?/td> 871K
代理商: V54C3128164VB6
41
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Complete List of Operation Commands
SDRAM Function Truth Table
CURRENT
STATE1
CS
RAS
CAS
WE
BS
Addr
ACTION
Idle
H
L
X
H
L
X
H
L
H
L
X
H
L
X
H
L
H
L
X
BS
X
Op-
X
RA
AP
X
Code
NOP or Power Down
NOP
ILLEGAL2
ILLEGAL
2
Row (&Bank) Active; Latch Row Address
NOP4
Auto-Refresh or Self-Refresh5
Mode reg. Access5
Row Active
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
X
BS
X
CA,AP
X
AP
X
NOP
Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP
ILLEGAL2
Precharge
ILLEGAL
Read
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
BS
X
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, New Read, DetermineAP3
Term Burst, Start Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge
ILLEGAL
Write
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
BS
X
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, Start Read, DetermineAP3
Term Burst, New Write, DetermineAP
3
ILLEGAL
2
Term Burst, Precharge3
ILLEGAL
Read
with
Auto
Precharge
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
BS
X
BS
X
AP
X
NOP (Continue Burst to End;> Precharge)
ILLEGAL
2
ILLEGAL
2
ILLEGAL
ILLEGAL2
ILLEGAL
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